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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
PM5347 S/UNITM
155-PLUS
SATURN USER NETWORK INTERFACE (155.52 MBIT/S & 51.84 MBIT/S, "PLUS")
DATA SHEET
ISSUE 6: JUNE 1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
PUBLIC REVISION HISTORY Issue No. 6 Issue Date June, 1998 Details of Change Data Sheet Reformatted -- No Change in Technical Content. Generated R6 data sheet from PMC940306, P8 Revision to Eng Doc P7 Revision to Eng Doc P5
5 4 3 2 1
Sept 24, 1996 Sept 29, 1995 June 1995 Nov. 1994 April, 1994
Creation of Document
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
CONTENTS 1 2 3 4 5 6 7 8 9 FEATURES ............................................................................................... 1 APPLICATIONS ........................................................................................ 1 REFERENCES ......................................................................................... 1 APPLICATION EXAMPLES ...................................................................... 1 BLOCK DIAGRAM.................................................................................... 1 DESCRIPTION ......................................................................................... 1 PIN DIAGRAM .......................................................................................... 1 PIN DESCRIPTION .................................................................................. 1 FUNCTIONAL DESCRIPTION ................................................................. 1 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 CLOCK RECOVERY...................................................................... 1 SERIAL TO PARALLEL CONVERTER........................................... 1 RECEIVE SECTION OVERHEAD PROCESSOR.......................... 1 RECEIVE LINE OVERHEAD PROCESSOR ................................. 1 TRANSPORT OVERHEAD EXTRACT PORT................................ 1 RECEIVE PATH OVERHEAD PROCESSOR ................................. 1 PATH OVERHEAD EXTRACT........................................................ 1 RECEIVE ATM CELL PROCESSOR ............................................. 1 CLOCK SYNTHESIS ..................................................................... 1 PARALLEL TO SERIAL CONVERTER........................................... 1 TRANSMIT SECTION OVERHEAD PROCESSOR ....................... 1 TRANSMIT LINE OVERHEAD PROCESSOR ............................... 1
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
9.13 9.14 9.15 9.16 9.17
TRANSPORT OVERHEAD INSERT PORT ................................... 1 TRANSMIT PATH OVERHEAD PROCESSOR .............................. 1 PATH OVERHEAD INSERT ........................................................... 1 TRANSMIT ATM CELL PROCESSOR........................................... 1 SONET/SDH SECTION AND PATH TRACE BUFFERS................. 1 9.17.1 RECEIVE TRACE BUFFER (RTB) ...................................... 1 9.17.2 TRANSMIT TRACE BUFFER (TTB).................................... 1
9.18
DROP SIDE INTERFACE .............................................................. 1 9.18.1 RECEIVE INTERFACE........................................................ 1 9.18.2 TRANSMIT INTERFACE ..................................................... 1
9.19 9.20 9.21 9.22 10 11
PARALLEL I/O PORT..................................................................... 1 JTAG TEST ACCESS PORT .......................................................... 1 MICROPROCESSOR INTERFACE ............................................... 1 REGISTER MEMORY MAP ........................................................... 1
NORMAL MODE REGISTER DESCRIPTION.......................................... 1 TEST FEATURES DESCRIPTION ........................................................... 1 11.1 11.2 11.3 TEST MODE REGISTER MEMORY MAP ..................................... 1 TEST MODE 0 DETAILS................................................................ 1 JTAG TEST PORT.......................................................................... 1
12
OPERATION ............................................................................................. 1 12.1 12.2 12.3 BOARD DESIGN RECOMMENDATIONS ...................................... 1 INTERFACING TO ECL OR PECL DEVICES ................................ 1 DRIVING DIFFERENTIAL INPUTS SINGLE ENDED.................... 1
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
12.4 12.5 12.6 12.7 12.8 13
CLOCK RECOVERY...................................................................... 1 ATM MAPPING AND OVERHEAD BYTE USAGE ......................... 1 CELL DATA STRUCTURE.............................................................. 1 BIT ERROR RATE MONITOR........................................................ 1 JTAG SUPPORT ............................................................................ 1
FUNCTIONAL TIMING ............................................................................. 1 13.1 13.2 13.3 13.4 OVERHEAD ACCESS ................................................................... 1 GFC ACCESS................................................................................ 1 DROP SIDE RECEIVE INTERFACE.............................................. 1 DROP SIDE TRANSMIT INTERFACE ........................................... 1
14 15 16 17 18 19
ABSOLUTE MAXIMUM RATINGS............................................................ 1 D.C. CHARACTERISTICS ........................................................................ 1 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS .......... 1 S/UNI-PLUS TIMING CHARACTERISTICS.............................................. 1 ORDERING AND THERMAL INFORMATION .......................................... 1 MECHANICAL INFORMATION................................................................. 1
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
LIST OF REGISTERS REGISTER 0X00: S/UNI-PLUS MASTER RESET AND IDENTITY / LOAD PERFORMANCE METERS...................................................................... 1 REGISTER 0X01: S/UNI-PLUS MASTER CONFIGURATION ............................ 1 REGISTER 0X02: S/UNI-PLUS MASTER INTERRUPT STATUS ....................... 1 REGISTER 0X03: S/UNI-PLUS MASTER CONTROL ........................................ 1 REGISTER 0X04: S/UNI-PLUS MASTER AUTO ALARM/MONITOR ................. 1 REGISTER 0X05: S/UNI-PLUS CLOCK SYNTHESIS CONTROL AND STATUS1 REGISTER 0X06: S/UNI-PLUS CLOCK RECOVERY CONTROL AND STATUS 1 REGISTER 0X07: S/UNI-PLUS PARALLEL I/O PORT ....................................... 1 REGISTER 0X08: S/UNI-PLUS PARALLEL INPUT PORT INTERRUPT ............ 1 REGISTER 0X09: S/UNI-PLUS PARALLEL INPUT PORT ENABLE .................. 1 REGISTER 0X0A: S/UNI-PLUS TRANSMIT J0/Z0 ............................................. 1 REGISTER 0X0B: S/UNI-PLUS APS CONTROL/STATUS.................................. 1 REGISTER 0X0C: S/UNI-PLUS RECEIVE K1 .................................................... 1 REGISTER 0X0D: S/UNI-PLUS RECEIVE K2 .................................................... 1 REGISTER 0X0E: S/UNI-PLUS RECEIVE S1 .................................................... 1 REGISTER 0X0F: S/UNI-PLUS TRANSMIT S1 .................................................. 1 REGISTER 0X10: RSOP CONTROL/INTERRUPT ENABLE.............................. 1 REGISTER 0X11: RSOP STATUS/INTERRUPT STATUS ................................... 1 REGISTER 0X12: RSOP SECTION BIP-8 LSB .................................................. 1 REGISTER 0X13: RSOP SECTION BIP-8 MSB ................................................. 1
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
REGISTER 0X14: TSOP CONTROL................................................................... 1 REGISTER 0X15: TSOP DIAGNOSTIC .............................................................. 1 REGISTER 0X18: RLOP CONTROL/STATUS..................................................... 1 REGISTER 0X19: RLOP INTERRUPT ENABLE/INTERRUPT STATUS ............. 1 REGISTER 0X1A: RLOP LINE BIP-24/8 LSB ..................................................... 1 REGISTER 0X1B: RLOP LINE BIP-24/8............................................................. 1 REGISTER 0X1C: RLOP LINE BIP-24/8 MSB.................................................... 1 REGISTER 0X1D: RLOP LINE FEBE LSB ......................................................... 1 REGISTER 0X1E: RLOP LINE FEBE ................................................................. 1 REGISTER 0X1F: RLOP LINE FEBE MSB......................................................... 1 REGISTER 0X20: TLOP CONTROL ................................................................... 1 REGISTER 0X21: TLOP DIAGNOSTIC .............................................................. 1 REGISTER 0X22: TLOP TRANSMIT K1 ............................................................. 1 REGISTER 0X23: TLOP TRANSMIT K2 ............................................................. 1 REGISTER 0X28: SSTB CONTROL ................................................................... 1 REGISTER 0X29: SSTB SECTION TRACE IDENTIFIER STATUS..................... 1 REGISTER 0X2A: SSTB INDIRECT ADDRESS REGISTER.............................. 1 REGISTER 0X2B: SSTB INDIRECT DATA REGISTER....................................... 1 REGISTER 0X30: RPOP STATUS/CONTROL .................................................... 1 REGISTER 0X31: RPOP INTERRUPT STATUS ................................................. 1 REGISTER 0X32: RPOP POINTER INTERRUPT STATUS ................................ 1 REGISTER 0X33: RPOP INTERRUPT ENABLE ................................................ 1 REGISTER 0X34: RPOP POINTER INTERRUPT ENABLE ............................... 1
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
REGISTER 0X35: RPOP POINTER LSB ............................................................ 1 REGISTER 0X36: RPOP POINTER MSB AND RDI FILTER CONTROL ............ 1 REGISTER 0X37: RPOP PATH SIGNAL LABEL................................................. 1 REGISTER 0X38: RPOP PATH BIP-8 LSB ......................................................... 1 REGISTER 0X39: RPOP PATH BIP-8 MSB ........................................................ 1 REGISTER 0X3A: RPOP PATH FEBE LSB......................................................... 1 REGISTER 0X3B: RPOP PATH FEBE MSB........................................................ 1 REGISTER 0X3C: RPOP AUXILIARY RDI.......................................................... 1 REGISTER 0X3D: RPOP ERROR EVENT CONTROL ....................................... 1 REGISTER 0X40: TPOP CONTROL/DIAGNOSTIC............................................ 1 REGISTER 0X41: TPOP POINTER CONTROL .................................................. 1 REGISTER 0X43: TPOP CURRENT POINTER LSB .......................................... 1 REGISTER 0X44: TPOP CURRENT POINTER MSB ......................................... 1 REGISTER 0X45: TPOP ARBITRARY POINTER LSB ....................................... 1 REGISTER 0X46: TPOP ARBITRARY POINTER MSB ...................................... 1 REGISTER 0X47: TPOP PATH TRACE ............................................................... 1 REGISTER 0X48: TPOP PATH SIGNAL LABEL ................................................. 1 REGISTER 0X49: TPOP PATH STATUS.............................................................. 1 REGISTER 0X4A: TPOP PATH USER CHANNEL .............................................. 1 REGISTER 0X4B: TPOP PATH GROWTH #1 (Z3).............................................. 1 REGISTER 0X4C: TPOP PATH GROWTH #2 (Z4).............................................. 1 REGISTER 0X4D: TPOP PATH GROWTH #3 (Z5).............................................. 1 REGISTER 0X50: RACP CONTROL................................................................... 1
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
REGISTER 0X51: RACP INTERRUPT STATUS.................................................. 1 REGISTER 0X52: RACP INTERRUPT ENABLE/CONTROL .............................. 1 REGISTER 0X53: RACP MATCH HEADER PATTERN ....................................... 1 REGISTER 0X54: RACP MATCH HEADER MASK............................................. 1 REGISTER 0X55: RACP CORRECTABLE HCS ERROR COUNT (LSB) ........... 1 REGISTER 0X56: RACP CORRECTABLE HCS ERROR COUNT (MSB) .......... 1 REGISTER 0X57: RACP UNCORRECTABLE HCS ERROR COUNT (LSB) ...... 1 REGISTER 0X58: RACP UNCORRECTABLE HCS ERROR COUNT (MSB) ..... 1 REGISTER 0X59: RACP RECEIVE CELL COUNTER (LSB) ............................. 1 REGISTER 0X5A: RACP RECEIVE CELL COUNTER ....................................... 1 REGISTER 0X5B: RACP RECEIVE CELL COUNTER (MSB) ............................ 1 REGISTER 0X5C: RACP GFC CONTROL AND MISCELLANEOUS CONTROL1 REGISTER 0X60: TACP CONTROL/STATUS...................................................... 1 REGISTER 0X61: TACP IDLE/UNASSIGNED CELL HEADER PATTERN ...... 1 REGISTER 0X62: TACP IDLE/UNASSIGNED CELL PAYLOAD OCTET PATTERN.................................................................................................. 1 REGISTER 0X63: TACP FIFO CONTROL........................................................... 1 REGISTER 0X64: TACP TRANSMIT CELL COUNTER (LSB) ............................ 1 REGISTER 0X65: TACP TRANSMIT CELL COUNTER ...................................... 1 REGISTER 0X66: TACP TRANSMIT CELL COUNTER (MSB) ........................... 1 REGISTER 0X67: TACP FIXED STUFF / GFC ................................................... 1 REGISTER 0X68: SPTB CONTROL ................................................................... 1 REGISTER 0X69: SPTB PATH TRACE IDENTIFIER STATUS ............................ 1
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
REGISTER 0X6A: SPTB INDIRECT ADDRESS REGISTER.............................. 1 REGISTER 0X6B: SPTB INDIRECT DATA REGISTER....................................... 1 REGISTER 0X6C: SPTB EXPECTED PATH SIGNAL LABEL............................. 1 REGISTER 0X6D: SPTB PATH SIGNAL LABEL STATUS ................................... 1 REGISTER 0X70: BERM CONTROL .................................................................. 1 REGISTER 0X71: BERM INTERRUPT ............................................................... 1 REGISTER 0X72: BERM LINE BIP ACCUMULATION PERIOD LSB ................. 1 REGISTER 0X73: BERM LINE BIP ACCUMULATION PERIOD MSB ................ 1 REGISTER 0X74: BERM LINE BIP THRESHOLD LSB ...................................... 1 REGISTER 0X75: BERM LINE BIP THRESHOLD MSB ..................................... 1 REGISTER 0X80: MASTER TEST ...................................................................... 1
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
LIST OF FIGURES FIGURE 1 - TYPICAL STS-3C ATM SWITCH PORT INTERFACE .................... 1 FIGURE 2 - APPLICATION WITH CLOCK RECOVERY & CLOCK SYNTHESIS BYPASSED ......................................................................................................... 1 FIGURE 3 - STS-3C/STM-1 AND STS-1 JITTER TOLERANCE........................ 1 FIGURE 4 - POINTER INTERPRETATION STATE DIAGRAM ........................... 1 FIGURE 5 - CELL DELINEATION STATE DIAGRAM......................................... 1 FIGURE 6 - HCS VERIFICATION STATE DIAGRAM ......................................... 1 FIGURE 7 - STS-3C DEFAULT TRANSPORT OVERHEAD VALUES ................ 1 FIGURE 8 - STS-1 DEFAULT TRANSPORT OVERHEAD VALUES................... 1 FIGURE 9 - DEFAULT PATH OVERHEAD VALUES ........................................... 1 FIGURE 10- INTERFACING S/UNI-PLUS TO ECL OR PECL ............................ 1 FIGURE 11- SINGLE ENDED DRIVING DIFFERENTIAL INPUTS .................... 1 FIGURE 12- ........................................................................................................ 1 FIGURE 13- STS-1 MAPPING............................................................................ 1 FIGURE 14- STS-3C (STM-1) MAPPING ........................................................... 1 FIGURE 15- 16-BIT WIDE, 27 WORD STRUCTURE.......................................... 1 FIGURE 16- 8-BIT WIDE, 53 WORD STRUCTURE............................................ 1 FIGURE 17- BOUNDARY SCAN ARCHITECTURE............................................ 1 FIGURE 18- TAP CONTROLLER FINITE STATE MACHINE .............................. 1 FIGURE 19- INPUT OBSERVATION CELL (IN_CELL) ....................................... 1 FIGURE 20- OUTPUT CELL (OUT_CELL)......................................................... 1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
FIGURE 21- BIDIRECTIONAL CELL (IO_CELL)................................................ 1 FIGURE 22- TRANSPORT OVERHEAD EXTRACTION..................................... 1 FIGURE 23- TRANSPORT OVERHEAD ORDERWIRE AND USER CHANNEL EXTRACTION ..................................................................................................... 1 FIGURE 24- TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA EXTRACTION ..................................................................................................... 1 FIGURE 25- PATH OVERHEAD EXTRACTION .................................................. 1 FIGURE 26- TRANSPORT OVERHEAD INSERTION ........................................ 1 FIGURE 27- TRANSPORT OVERHEAD ORDERWIRE AND USER CHANNEL INSERTION......................................................................................................... 1 FIGURE 28- TRANSPORT OVERHEAD DATA LINK CLOCK AND DATA INSERTION......................................................................................................... 1 FIGURE 29- PATH OVERHEAD INSERTION...................................................... 1 FIGURE 30- GFC EXTRACTION PORT ............................................................. 1 FIGURE 31- GFC INSERTION PORT................................................................. 1 FIGURE 32- RECEIVE SYNCHRONOUS FIFO, TSEN=0 .................................. 1 FIGURE 33- RECEIVE SYNCHRONOUS FIFO, TSEN=1 .................................. 1 FIGURE 34- TRANSMIT SYNCHRONOUS FIFO ............................................... 1 FIGURE 35- MICROPROCESSOR INTERFACE READ TIMING........................ 1 FIGURE 36- MICROPROCESSOR INTERFACE WRITE TIMING ...................... 1 FIGURE 37- LINE SIDE RECEIVE INTERFACE TIMING ................................... 1 FIGURE 38- RECEIVE ALARM OUTPUT TIMING ............................................. 1 FIGURE 39- RECEIVE OVERHEAD ACCESS TIMING...................................... 1 FIGURE 40- RECEIVE GFC ACCESS TIMING .................................................. 1
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
FIGURE 41- LINE SIDE TRANSMIT INTERFACE TIMING................................. 1 FIGURE 42- TRANSMIT ALARM INPUT TIMING ............................................... 1 FIGURE 43- TRANSMIT OVERHEAD ACCESS TIMING.................................... 1 FIGURE 44- TRANSMIT GFC ACCESS TIMING................................................ 1 FIGURE 45- DROP SIDE RECEIVE INTERFACE TIMING, TSEN = 0 ............... 1 FIGURE 46- DROP SIDE RECEIVE INTERFACE TIMING, TSEN = 1 ............... 1 FIGURE 47- DROP SIDE TRANSMIT INTERFACE............................................ 1 FIGURE 48- JTAG PORT INTERFACE TIMING.................................................. 1 FIGURE 49- 208 PIN PLASTIC QUAD FLAT PACK (R SUFFIX): ....................... 1
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 - ........................................................................................................ 1 - ........................................................................................................ 1 - ........................................................................................................ 1 - ........................................................................................................ 1 - ........................................................................................................ 1 - ........................................................................................................ 1 - ........................................................................................................ 1 - ........................................................................................................ 1
TABLE 10 - INSTRUCTION REGISTER............................................................ 1 TABLE 11 - ........................................................................................................ 1 TABLE 12 - S/UNI-PLUS ABSOLUTE MAXIMUM RATINGS ............................ 1 TABLE 13 - S/UNI-PLUS D.C. CHARACTERISTICS ......................................... 1 TABLE 14 - MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 35) . ......................................................................................................... 1 TABLE 15 - MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 36) ......................................................................................................... 1 TABLE 16 - LINE SIDE RECEIVE INTERFACE (FIGURE 37)........................... 1 TABLE 17 - RECEIVE ALARM OUTPUT (FIGURE 38)..................................... 1 TABLE 18 - RECEIVE OVERHEAD ACCESS (FIGURE 39) ............................. 1 TABLE 19 - RECEIVE GFC ACCESS (FIGURE 40).......................................... 1 TABLE 20 - LINE SIDE TRANSMIT INTERFACE (FIGURE 41) ........................ 1 TABLE 21 - TRANSMIT ALARM INPUT (FIGURE 42) ...................................... 1
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
TABLE 22 - TRANSMIT OVERHEAD ACCESS (FIGURE 43) ........................... 1 TABLE 23 - TRANSMIT GFC ACCESS (FIGURE 44) ....................................... 1 TABLE 24 - DROP SIDE RECEIVE INTERFACE (FIGURE 45, FIGURE 46).... 1 TABLE 25 - DROP SIDE TRANSMIT INTERFACE (FIGURE 47) ...................... 1 TABLE 26 - JTAG PORT INTERFACE (FIGURE 48) ......................................... 1 TABLE 27 - S/UNI-PLUS ORDERING INFORMATION ..................................... 1 TABLE 28 - S/UNI-PLUS THERMAL INFORMATION........................................ 1
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
1
FEATURES * Monolithic Saturn User Network Interface that implements the ATM physical layer for Broadband ISDN according to ANSI, ITU, and ATM Forum specifications. Processes duplex 155.52 Mbit/s STS-3c/STM-1 or 51.84 Mbit/s STS-1 data streams with on-chip clock and data recovery and clock synthesis. Provides Saturn Compliant Interface - PHYsical layer (SCI-PHYTM) FIFO buffers in both transmit and receive paths with parity support. Provides a generic 8-bit microprocessor bus interface for configuration, control, and status monitoring. Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. Low power, +5 Volt, CMOS technology. 208 pin high performance plastic quad flat pack (PQFP) 28 mm x 28 mm package. Industrial temperature range operation (-40C to +85C).
* * * * * * *
The receiver section: * * * * * * Provides a serial interface at 155.52 or 51.84 Mbit/s. Recovers the clock and data. Frames to and descrambles the recovered stream. Filters and captures the automatic protection switch channel (K1, K2) bytes in readable registers and detects APS byte failure. Captures the synchronization status (S1) byte in a readable register. Interprets the received payload pointer (H1, H2) and extracts the STS-3c/1 (STM-1) synchronous payload envelope and path overhead.
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
*
Extracts ATM cells from the received STS-3c/1 (STM-1) synchronous payload envelope using ATM cell delineation and provides optional ATM cell payload descrambling, header check sequence (HCS) error detection and correction, and idle/unassigned cell filtering. Provides a generic 16 bit or 8 bit wide datapath interface to read extracted cells from an internal four cell FIFO buffer. Extracts all transport overhead bytes and serializes them at 5.184 Mbit/s for optional external processing. Extracts the section user channel (F1) and the orderwire channels (E1, E2) and serializes them into three independent 64 kbit/s streams for optional external processing. Extracts the data communication channels (D1-D3, D4-D12) and serializes them at 192 kbit/s (D1-D3) and 576 kbit/s (D4-D12) for optional external processing. Extracts all path overhead bytes and serializes them at 576 kbit/s for optional external processing. Extracts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence into internal register banks. Detects loss of signal (LOS), out of frame (OOF), loss of frame (LOF), line alarm indication signal (LAIS), line remote defect indication (LRDI), loss of pointer (LOP), path alarm indication signal (PAIS), path remote defect indication signal (PRDI) and loss of cell delineation (LCD). Counts received section BIP-8 (B1) errors, received line BIP-24/8 (B2) errors, line far end block errors (M0 or M1), received path BIP-8 (B3) errors and path far end block errors (G1) for performance monitoring purposes. Counts received cells written into the receive FIFO, received HCS errored cells that are discarded, and received HCS errored cells that are corrected and passed through the receive FIFO. Extracts and serializes the GFC field from all received cells (including idle/unassigned cells) for external processing.
* * *
*
* * *
*
*
*
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
The transmitter section: * * * * * * * * * * Provides an internal four cell FIFO into which cells are written using a generic 16-bit or 8-bit wide datapath interface. Inserts the generic flow control (GFC) bits via a simple serial interface and provides a transmit XOFF function to allow for local flow control. Counts transmit cells read from the transmit FIFO. Provides idle/unassigned cell insertion, HCS generation/insertion, and ATM cell payload scrambling. Inserts ATM cells into the transmitted STS-3c/1 (STM-1) synchronous payload envelope. Inserts a register programmable path signal label (C2). Generates the transmit payload pointer (H1, H2) and inserts the path overhead. Optionally inserts the 16 or 64 byte section trace (J0) sequence and the 16 or 64 byte path trace (J1) sequence from internal register banks. Optionally inserts externally generated path overhead bytes received via a 576 kbit/s serial interface. Optionally inserts externally generated data communication channels (D1-D3, D4-D12) via a 192 kbit/s (D1-D3) serial stream and a 576 kbit/s (D4-D12) serial stream. Optionally inserts externally generated section user channel (F1) and externally generated orderwire channels (E1, E2) via three 64 kbit/s serial interfaces. Optionally inserts externally generated transport overhead bytes received via a 5.184 Mbit/s serial interface. Scrambles the transmitted STS-3c/1 (STM-1) stream and inserts the framing bytes (A1, A2).
*
* *
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
* * *
Synthesizes the 155.52 MHz or 51.84 MHz transmit clock from a 19.44 MHz or 6.48 MHz reference. Provides a serial interface at 155.52 Mbit/s or 51.84 Mbit/s. Optionally inserts path alarm indication signal (PAIS), path remote defect indication (PRDI), line alarm indication signal (LAIS) and line remote defect indication (LRDI) indication. Optionally inserts register programmable APS (K1, K2) and synchronization status (S1) bytes. Inserts path BIP-8 codes (B3), path far end block error (G1) indications, line BIP-24/8 codes (B2), line far end block error (M0 or M1) indications, section BIP-8 codes (B1) to allow performance monitoring at the far end. Allows forced insertion of all zeros data (after scrambling), the corruption of the framing bytes or the corruption of the section, line, or path BIP-8 codes for diagnostic purposes.
* *
*
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
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APPLICATIONS * * * * SONET/SDH Based ATM Switching Systems SONET/SDH Based ATM Terminals B-ISDN User Network Interfaces B-ISDN Test Equipment
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PM5347 S/UNI-PLUS
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REFERENCES 1. ITU Recommendation G.709 DRAFT - "Synchronous Multiplexing Structure", COM XVIII-R 105-E. 2. ITU Recommendation I.432 DRAFT - "B-ISDN User-Network Interface-Physical Interface Specification", COM XVIII-R 80-E. 3. Bell Communications Research - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 1, December 1994. 4. ATM Forum - ATM User-Network Interface Specification, V3.0, October, 1993. 5. ATM Forum - BISDN Inter Carrier Interface Specification, V1.0, August, 1993. 6. IEEE 1149.1 - Standard Test Access Port and Boundary Scan Architecture, May 21, 1990. 7. T1.105, American National Standard for Telecommunications - Digital Hierarchy - Optical Interface Rates and Formats Specifications (SONET), 1991 8. T1X1.3/93-006R3, Draft American National Standard for Telecommunications, Synchronous Optical Network (SONET): Jitter at Network Interfaces 9. T1E1.2/94-002R1, Draft American National Standard for Telecommunications, Broadband ISDN and DS1/ATM User Network Interfaces: Physical Layer Specification
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PM5347 S/UNI-PLUS
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4
APPLICATION EXAMPLES The S/UNI-PLUS is used to implement the core physical layer functions of an ATM User Network Interface or BISDN Inter Carrier Interface. The S/UNI-PLUS may find application at either end of switch-to-switch links or switch-to-terminal links, both in public network (WAN) and private network (LAN) situations. In a typical STS-3c (STM-1) application, the S/UNI-PLUS performs clock and data recovery for the receive direction and clock synthesis for the transmit direction of the line interface. On the drop side, the S/UNI-PLUS interfaces directly with ATM layer processors and switching or adaptation functions using a SCI-PHYTM synchronous FIFO style interface. The initial configuration and ongoing control and monitoring of the S/UNI-PLUS are normally provided via a generic microprocessor interface. This application is shown in Figure 1. Figure 1 - Typical STS-3c ATM Switch Port Interface
TRANSMIT OVERHEAD INSERT TRANSMIT ALARM INSERT SIGNALS
Ref. Clock
19.44 MHz
TRCLK+/-
TCA TXPRTY[1:0] TDAT[15:0] TSOC TWRENB
E/O
TXD+/-
PM5347 S/UNI-PLUS SONET/SDH USER NETWORK INTERFACE
RRCLK+/-
TFCLK RCA RXPRTY[1:0] RDAT[15:0] RSOC RRDENB RFCLK
TRANSMIT ATM PROCESS SWITCHING NETWORK RECEIVE ATM PROCESS
O/E
RXD+/ALOS+/-
RECEIVE OVERHEAD EXTRACT
RECEIVE ALARM DETECT SIGNALS
MICRO BUS FOR CONFIG, STATUS AND CONTROL
The clock recovery function of the S/UNI-PLUS may by bypassed. This is useful in applications where clock recovery is not required such as when optical receivers are utilized that have integral clock recovery. Similarly, the clock synthesis function of the S/UNI-PLUS may be bypassed. This is useful in applications where clock synthesis is not required, for example where a 155 MHz transmit clock source is available. An example of an application where clock recovery and clock synthesis are bypassed is shown in Figure 2.
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Figure 2 Bypassed
- Application With Clock Recovery & Clock Synthesis
Ref. Clock
155.52 MHz
TRANSMIT OVERHEAD INSERT
TRANSMIT ALARM INSERT SIGNALS
TRCLK+/-
TCA TXPRTY[1:0] TDAT[15:0] TSOC TWRENB
E/O
TXD+/-
PM5347 S/UNI-PLUS SONET/SDH USER NETWORK INTERFACE O/E With Clock Recovery
TFCLK RCA RXPRTY[1:0] RDAT[15:0] RSOC RRDENB RFCLK
TRANSMIT ATM PROCESS SWITCHING NETWORK RECEIVE ATM PROCESS
RRCLK+/RXD+/ALOS+/-
RECEIVE OVERHEAD EXTRACT
RECEIVE ALARM DETECT SIGNALS
MICRO BUS FOR CONFIG, STATUS AND CONTROL
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
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BLOCK DIAGRAM Normal Operating Mode
TLAIS TSDCLK,TOWCLK TSD,TSOW,TSUC
TLRDI TLDCLK TLD,TLOW
TTOH TTOHFP TTOHCLK TTOHEN
TPOH TPOHFP TPOHCLK TPOHEN
TOHFP TFP GTOCLK
POP[3:0] PIP[3:0]
TPAIS TPRDI
Transport O/H Insert
Path O/H Insert
Parallel Input/Output Port
TCP TGFC XOFF
TDO TDI TCK TMS TRSTB JTAG Test Access Port TSOC TDAT[15:0] TXPRTY[1:0] TCA TWRENB TFCLK RSOC RDAT[15:0] RXPRTY[1:0] RCA RRDENB RFCLK Drop Side I/F BUS8 TSEN
TRCLK+/TXD+/TXC+/RXDO+/RXD+/ALOS+/RRCLK+/-
Clock Synthesizer PISO
TATP TBYP
Clock Recovery SIPO
Tx Section O/H Processor Section Trace Buffer Rx Section O/H Processor
Tx Line O/H Processor
Tx Path O/H Processor Path Trace Buffer Rx Path O/H Processor
Tx ATM Cell Processor
Tx ATM 4 Cell FIFO
Rx Line O/H Processor
Rx ATM Cell Processor
Rx ATM 4 Cell FIFO
Transport O/H Extract LF+/LFO RATP RBYP
Path O/H Extract
Microprocessor I/F
LOS LOF RSDCLK,ROWCLK RSD,RSOW,RSUC
LAIS LRDI RLDCLK RLD,RLOW RTOH RTOHFP RTOHCLK
RPOH RPOHFP RPOHCLK
D[7:0] A[7:0] ALE CSB WRB RDB RSTB INTB
LOP PRDI PAIS
LCD
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ROHFP GROCLK
RCP RGFC
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Loopback Modes
Transport O/H Insert
Path O/H Insert
Parallel Input/Output Port
JTAG Test Access Port
Clock Synthesizer PISO SERIAL LINE LOOPBACK Clock Recovery SIPO
Tx Section O/H Processor Section SERIAL Trace DIAGNOSTIC Buffer LOOPBACK Rx Section O/H Processor
Tx Line O/H Processor
Tx Path O/H Processor
Tx ATM Cell Processor
Rx Line O/H Processor
Path PARALLEL Trace DIAGNOSTIC Buffer LOOPBACK Rx Path O/H Rx ATM Cell Processor Processor
Tx ATM 4 Cell FIFO Drop Side I/F
Rx ATM 4 Cell FIFO
Transport O/H Extract
Path O/H Extract
Microprocessor I/F
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
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DESCRIPTION The PM5347 S/UNI-PLUS SATURN User Network Interface is a monolithic integrated circuit that implements the SONET/SDH processing and ATM mapping functions of a 155 or 51 Mbit/s ATM User Network Interface. The S/UNI-PLUS receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. It performs framing (A1, A2), descrambling, detects alarm conditions, and monitors section, line, and path bit interleaved parity (B1, B2, B3), accumulating error counts at each level for performance monitoring purposes. Line and path far end block error indications (M0 or M1, G1) are also accumulated. The S/UNI-PLUS interprets the received payload pointers (H1, H2) and extracts the synchronous payload envelope which carries the received ATM cell payload. In addition to its basic processing of the received SONET/SDH overhead, the S/UNI-PLUS provides convenient access to all overhead bytes, which are extracted and serialized on lower rate interfaces, allowing additional external processing of overhead, if desired. The S/UNI-PLUS frames to the ATM payload using cell delineation. HCS error correction is provided. Idle/unassigned cells may be dropped according to a programmable filter. Cells are also dropped upon detection of an uncorrectable header check sequence error. The ATM cell payloads are descrambled. The ATM cells that are passed are written to a four cell FIFO buffer. The received cells are read from the FIFO using a generic 16- or 8-bit wide datapath interface. Counts of received ATM cell headers that are errored and uncorrectable and also those that are errored and correctable are accumulated independently for performance monitoring purposes. The S/UNI-PLUS transmits SONET/SDH streams using a bit serial interface and formats section, line, and path overhead appropriately. It synthesizes the transmit clock from a lower frequency reference and performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section, line, and path bit interleaved parity (B1, B2, B3) as required to allow performance monitoring at the far end. Line and path far end block error indications (M0 or M1, G1) are also inserted. The S/UNI-PLUS generates the payload pointer (H1, H2) and inserts the synchronous payload envelope which carries the ATM cell payload. In addition to its basic formatting of the transmitted SONET/SDH overhead, the S/UNI-PLUS provides convenient access to all overhead bytes, which are optionally inserted from lower rate serial interfaces, allowing external sourcing of overhead, if desired. The S/UNI-PLUS also supports the insertion of
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
a large variety of errors into the transmit stream, such as framing pattern errors, bit interleaved parity errors, and illegal pointers, which are useful for system diagnostics and tester applications. ATM cells are written to an internal four cell FIFO using a generic 16- or 8-bit wide datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one cell. The S/UNI-PLUS provides generation of the header check sequence and scrambles the payload of the ATM cells. Each of these transmit ATM cell processing functions can be enabled or bypassed. No line rate clocks are required directly by the S/UNI-PLUS as it synthesizes the transmit clock and recovers the receive clock using a 19.44 MHz or 6.48 MHz reference clock. Optionally, receive clock recovery or transmit clock synthesis may be bypassed. The S/UNI-PLUS is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. The S/UNI-PLUS also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. The S/UNI-PLUS is implemented in low power, +5 Volt, CMOS technology. It has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible outputs and is packaged in a 208 pin PQFP package.
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
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PIN DIAGRAM The S/UNI-PLUS is packaged in a 208 pin plastic QFP package having a body size of 28 mm by 28 mm and a pin pitch of 0.5 mm.
PIN 208
RDAT[8] VSS_DC VDD_DC RDAT[7] RDAT[6] RDAT[5] RDAT[4] VSS_AC VDD_AC RDAT[3] VSS_DC VDD_DC RDAT[2] RDAT[1] RDAT[0] RXPRTY[1] RXPRTY[0] RFCLK RRDENB RSOC RCA GROCLK LOS LOF VSS_AC VDD_AC LOP LCD PAIS PRDI VSS_DC VDD_DC LAIS LRDI RCP RGFC ROHFP RPOH RPOHFP RPOHCLK RTOH RTOHFP VSS_AC VDD_AC RTOHCLK RSOW RSUC VSS_DC VDD_DC RLD RLDCLK RSD
PIN 1
RDAT[9] RDAT[10] RDAT[11] VDD_AC VSS_AC RDAT[12] VDD_DC VSS_DC RDAT[13] RDAT[14] RDAT[15] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] ALE RSTB CSB WRB RDB INTB TRSTB D[0] D[1] VDD_DC VSS_DC D[2] D[3] VDD_AC VSS_AC D[4] D[5] VDD_DC VSS_DC D[6] D[7] TDO TDI TMS TSEN BUS8 TCK TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] Index
PIN 157 PIN 156
RSDCLK ROWCLK RLOW RBYP RATP LF+ LFLFO RAVS1 RAVD1 RAVS2 RAVD2 RAVS4 RRCLKRRCLK+ RAVD4 RAVD3 RAVS3 ALOSALOS+ RXDRXD+ VSS_AC VDD_AC RXDORXDO+ VSS_DC VDD_DC TXVSS TXDTXD+ TXCTXC+ TXVDD TAVS3 TRCLKTRCLK+ TAVD3 TAVS2 TAVD2 TAVS1 TAVD1 TATP TBYP PIP[0] PIP[1] PIP[2] PIP[3] POP[0] POP[1] POP[2] POP[3]
PM5347 S/UNI-PLUS
PIN 52
TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] VDD_DC VSS_DC TDAT[13] TDAT[14] TDAT[15] TXPRTY[0] TXPRTY[1] TFCLK TWRENB TSOC TCA XOFF GTOCLK TPAIS TPRDI TLAIS TLRDI TCP TGFC VSS_DC VDD_DC TFP VDD_AC VSS_AC TOHFP TPOH TPOHFP TPOHEN TPOHCLK TTOH TTOHFP TTOHEN TTOHCLK TSOW TSUC TLOW TOWCLK VDD_AC VDD_DC VSS_DC VSS_AC TLD TLDCLK TSD TSDCLK
PIN 105 PIN 53 PIN 104
13
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
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PIN DESCRIPTION Pin Name RBYP Type Input Pin No. 153 Function The receive bypass (RBYP) input disables clock recovery. If RBYP is high, RXD+/- is sampled on the rising edge of RRCLK+/-. If RBYP is low, the receive clock is recovered from the RXD+/- bit stream. RBYP requires an external pull-down resistor. The receive differential data inputs (RXD+, RXD-) contain the NRZ bit serial receive stream. RXD+/is sampled on the rising edge of RRCLK+/- when clock recovery is bypassed (the falling edge may be used by reversing RRCLK+/-), otherwise the receive clock is recovered from the RXD+/- bit stream. Please refer to the Operation section for a discussion of PECL interfacing issues. The receive differential data outputs (RXDO+, RXDO-) are sliced versions of the RXD+ and RXD- inputs. These outputs are provided to allow decision feedback equalization (DFE) to correct baseline wander. It is intended that these outputs be low pass filtered and attenuated to create an appropriate correction signal that is summed with incoming data to recover the low frequency components. The receive differential reference clock inputs (RRCLK+, RRCLK-) must be a jitter-free 19.44 MHz or 6.48 MHz reference clock when clock recovery is enabled. When clock recovery is bypassed, RRCLK+/- is nominally a 155.52 MHz or 51.84 MHz 50% duty cycle clock and provides timing for the S/UNI-PLUS receive functions. In this case, RXD+/- is sampled on the rising edge of RRCLK+/-. Please refer to the Operation section for a discussion of PECL interfacing issues.
RXD+ RXD-
PECL Input
135 136
RXDO+ RXDO-
Output
131 132
RRCLK+ RRCLK-
PECL Input
142 143
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name ALOS+ ALOS-
Type PECL Input
Pin No. 137 138
Function The analog loss of signal (ALOS+/-) differential inputs are used to indicate a loss of receive signal power. When ALOS+/- is asserted, the data on the receive data (RXD+/-) pins is forced to all zeros and the phase locked loop switches to the reference clock (RRCLK+/-) to keep the recovered clock in range. These inputs must be DC coupled. Please refer to the Operation section for a discussion of PECL interfacing issues. This analog test point (RATP) is provided for production test purposes. Connect this pin to ground. Passive components connected to the recovery loop filter (LF+, LF- and LFO) pins determine the dynamics of the clock recovery unit. Refer to the Operation section for details. If the transmit bypass (TBYP) input is high, transmit clock synthesis is disabled and TRCLK+/becomes the line rate clock of 155.52 MHz or 51.84 MHz. If TBYP is low, the transmit clock is synthesized from a 19.44 MHz or 6.48 MHz reference. TBYP requires an external pull down resistor. The transmit differential reference clock inputs (TRCLK+, TRCLK-) must be a jitter-free 19.44 MHz or 6.48 MHz reference clock when clock synthesis is enabled. When clock synthesis is bypassed, TRCLK+/- is nominally a 155.52 MHz or 51.84 MHz 50% duty cycle clock. This clock provides timing for the S/UNI-PLUS transmit functions. TRCLK+/- may be left unconnected when S/UNI-PLUS loop timing is enabled, or when the transmit clock is synthesized from the receive reference (RRCLK+/-). Please refer to the Operation section for a discussion of PECL interfacing issues.
RATP
Analog
152
LF+, LF-, LFO TBYP
Analog
151 150 149
Input
113
TRCLK+ TRCLK-
PECL Input
120 121
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TXD+ TXDTXC+ TXC-
Type Output
Pin No. 126 127
Function The transmit differential data outputs (TXD+, TXD) contain the transmit stream. TXD+/- is updated on the falling edge of TXC+/The transmit clock (TXC+, TXC-) outputs are available when the transmit data rate is 51.84 Mbit/s. TXD+/- is updated on the falling edge of TXC+ and on the rising edge of TXC-. When STS-3c (STM-1) is selected, TXC+ is held low and TXC- is held high. This analog test point (TATP) is provided for production test purposes. Connect this pin to ground. The generated receive clock (GROCLK) is nominally a 6.48 MHz or 19.44 MHz, 50% duty cycle clock. Receive outputs that are timed from the line are updated with timing aligned to GROCLK. When configured for receive clock recovery (RBYP low), GROCLK is the recovered line clock divided down by 8. When receive clock recovery is bypassed (RBYP high), GROCLK is equal to RRCLK+/- divided down by 8.
Output
124 125
TATP
Analog
114
GROCLK
Output
187
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TFP
Type Input
Pin No. 81
Function The active high transmit frame pulse (TFP) signal is used to align the SONET/SDH transport frame generated by the S/UNI-PLUS device to a system reference. TFP should be brought high for a single GTOCLK period every 810 (STS-1), or 2430 (STS-3c/STM-1) GTOCLK cycles or a multiple thereof. TFP may be tied low if such synchronization is not required. The offset between an active TFP input and the resultant frame alignment on TOHFP is 16 GTOCLK periods in STS-1 mode and 24 GTOCLK periods in STS-3c mode. TFP is sampled on the rising edge of GTOCLK. The generated transmit output clock (GTOCLK) is nominally a 6.48 MHz or 19.44 MHz, 50% duty cycle clock. Transmit inputs and outputs that are timed from the line are updated with timing aligned to GTOCLK. When configured for transmit clock synthesis (TBYP low), GTOCLK is the synthesized line clock divided by 8. When transmit clock synthesis is bypassed (TBYP high), GTOCLK is equal to TRCLK+/- divided by 8.
GTOCLK
Output
72
TOHFP
Output
84
The transmit overhead frame pulse (TOHFP) signal identifies the start of a byte on outputs TSOW, TSUC and TLOW. If required, TOHFP is one GTOCLK clock cycle wide and can be used as a reset pulse for an external counter. Please refer to the functional timing diagrams for details.
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name LOS
Type Output
Pin No. 186
Function The loss of signal (LOS) signal is set high when loss of signal is declared. This occurs when a violating period (20 3 s) of consecutive all zeros bytes is detected on the incoming STS-3c/1 (STM-1) signal (before descrambling). LOS is removed when two valid framing words (A1, A2) are detected and during the intervening time, no violating period of consecutive all zeros patterns is detected. This alarm indication is also available via register access. LOS is updated on the falling edge of GROCLK. The loss of frame (LOF) signal is set high when loss of frame is declared. This occurs when an out-of-frame condition persists for a period of 3 ms. LOF is removed when an in-frame condition persists for a period of 3 ms. This alarm indication is also available via register access. LOF is updated on the falling edge of GROCLK. The line alarm indication signal (LAIS) is set high when line AIS is declared. This occurs when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames (as selected in the RLOP Control/Status register). LAIS is removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. This alarm indication is also available via register access. LAIS is updated on the falling edge of GROCLK.
LOF
Output
185
LAIS
Output
176
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name LRDI
Type Output
Pin No. 175
Function The line remote defect indication (LRDI) signal is set high when line RDI is declared. This occurs when a 110 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames (as selected in the RLOP Control/Status register). LRDI is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. This alarm indication is also available via register access. LRDI is updated on the falling edge of GROCLK. The loss of pointer (LOP) signal is set high when loss of pointer is declared. This occurs when a valid pointer (H1, H2) is not found in eight consecutive frames, or if eight consecutive new data flags are detected. LOP is removed when the same valid and normal pointer with a normal new data flag is detected in three consecutive frames. The loss of pointer state is not entered if the receive stream contains path AIS. This alarm indication is also available via register access. LOP is updated on the falling edge of GROCLK. The path AIS (PAIS) signal is set high when path AIS is declared. This occurs when an all ones pattern is observed in the pointer bytes (H1, H2) for three consecutive frames. Path AIS is removed when the same valid and normal pointer is detected for three consecutive frames or a legal pointer with an active new data flag (NDF) is received. This alarm indication is also available via register access. PAIS is updated on the falling edge of GROCLK.
LOP
Output
182
PAIS
Output
180
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name PRDI
Type Output
Pin No. 179
Function The path remote defect indication (PRDI) signal is set high when path RDI is declared. This occurs when bit 5 of the path status byte (G1) is set high for five or ten consecutive frames. Path RDI is removed when bit 5 of the G1 byte is set low for five or ten consecutive frames (as selected in the RPOP Pointer MSB and RDI Filter Control register). This alarm indication is also available via register access. PRDI is updated on the falling edge of GROCLK. The loss of cell delineation (LCD) signal indicates when cell delineation can not be found. LCD transitions high when an out of cell delineation (OCD) anomaly has persisted for 4 ms. Once asserted, LCD remains high until no OCD anomaly has been detected for 4 ms at which time, LCD is set low. The OCD state is entered when the cell delineation state machine is not in the SYNC state. Please refer to the Functional Description section for an explanation of the cell delineation state machine. This alarm indication is also available via register access. LCD is updated on the falling edge of GROCLK.
LCD
Output
181
TLAIS
Input
75
The active high transmit line alarm indication (TLAIS) signal controls the insertion of line AIS. Line AIS is inserted by overwriting the SONET/SDH frame contents with all ones (before scrambling). The section overhead is not overwritten. This function can also be performed via register access. Line AIS insertion is internally synchronized to frame boundaries. The TLAIS input takes precedence over the TTOH and TTOHEN inputs. TLAIS is sampled on the rising edge of GTOCLK.
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TLRDI
Type Input
Pin No. 76
Function The active high transmit line remote defect indication (TLRDI) signal controls the insertion of line RDI. Line RDI is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the K2 byte. This function can also be performed via register access, or be enabled to occur automatically upon detection of receive line AIS, loss of signal, or loss of frame. The TLRDI input takes precedence over the TTOH and TTOHEN inputs. TLRDI is sampled on the rising edge of GTOCLK. The active high transmit path alarm indication (TPAIS) signal controls the insertion of STS-path AIS. A high level on TPAIS forces the insertion of an all ones pattern into the complete synchronous payload envelope, and the payload pointer bytes (H1, H2). Path AIS insertion is internally synchronized to SPE frame boundaries. This function can also be performed via register access. TPAIS is sampled on the rising edge of GTOCLK. The transmit path remote defect indication (TPRDI) signal controls the insertion of path RDI. A high level on TPRDI forces a logic one to be inserted in the path RDI bit position in the path status byte (G1). This function can also be performed via register access, or be enabled to occur automatically upon detection of receive line AIS, loss of frame, loss of signal, loss of pointer, or path AIS. The TPOH and TPOHEN inputs take precedence over the TPRDI input. TPRDI is sampled on the rising edge of GTOCLK.
TPAIS
Input
73
TPRDI
Input
74
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RFCLK
Type Input
Pin No. 191
Function The receive FIFO clock (RFCLK) is used to read words from the synchronous FIFO interface. RFCLK must cycle at a 52 MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflow. RRDENB is sampled using the rising edge of RFCLK. RSOC, RCA, RXPRTY[1:0] and RDAT[15:0] are updated on the rising edge of RFCLK. The active low receive read enable input (RRDENB) is used to initiate reads from the receive FIFO. When sampled low using the rising edge of RFCLK, a word is read from the internal synchronous FIFO and output on bus RDAT[15:0]. When sampled high using the rising edge of RFCLK, no read is performed and outputs RDAT[15:0], RXPRTY[1:0] and RSOC are tristated if the TSEN input is high. RRDENB must operate in conjunction with RFCLK to access the FIFO at a high enough instantaneous rate as to avoid FIFO overflows.
RRDENB
Input
190
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RXPRTY[0] RXPRTY[1]
Type Tristate
Pin No. 194 195 196 199 202 203 204 205 208 1 2 3 6 9 10 11
Function The receive cell data (RDAT[15:0]) bus carries the ATM cell octets that are read from the receive FIFO. When the 16-bit SCI-PHY interface is selected, (BUS8 is tied low), RDAT[15:0] contains the 16 bit wide word bus. When the 8-bit SCIPHY interface is selected (BUS8 is tied high), RDAT[7:0] contains the 8-bit wide word bus (RDAT[15:8] is not used). RDAT[15:0] is updated on the rising edge of RFCLK. When the S/UNI-PLUS is configured for tristate operation using the TSEN input, tristating of output bus RDAT[15:0] is controlled by input RRDENB.
Tristate
192 193
The receive parity (RXPRTY[1:0]) signals indicate the parity of the RDAT[15:0] bus. RXPRTY[1] is the parity calculation over the RDAT[15:8] bus. RXPRTY[0] is the parity calculation over the RDAT[7:0] bus. Alternately, the device can be configured so that RXPRTY[1] is the parity calculation over the entire RDAT[15:0] bus. RXPRTY[0] is not used in this case. Odd or even parity selection can be made using the RACP Control register. RXPRTY[1:0] is updated on the rising edge of RFCLK. When the S/UNI-PLUS is configured for tristate operation using the TSEN input, tristating of output bus RXPRTY[1:0] is control by input RRDENB.
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RSOC
Type Tristate
Pin No. 189
Function The receive start of cell (RSOC) signal marks the start of cell on the RDAT[15:0] bus. When RSOC is high, the first word of the cell structure is present on the RDAT[15:0] bus. RSOC is updated on the rising edge of RFCLK. When the S/UNI-PLUS is configured for tristate operation using the TSEN input, tristating of output RSOC is control by input RRDENB.
RCA
Output
188
The receive cell available (RCA) signal indicates when a cell is available in the receive FIFO. When asserted, RCA indicates that the receive FIFO has at least one cell available to be read. When RCA is deasserted, the receive FIFO contains only four words or is empty (as selected in the RACP Interrupt Enable/Control register). RCA default state can be selected in the S/UNI-PLUS Master Control register. RCA is updated on the rising edge of RFCLK. The active polarity of this signal is programmable and defaults to active high. The bus width select (BUS8) input selects the transmit and receive SCI-PHY interface types. When BUS8 is tied high, the 8-bit wide SCI-PHY interface is enabled. When BUS8 is tied low, the 16-bit wide SCI-PHY interface is selected. The tristate enable (TSEN) signal allows tristate control over outputs RDAT[15:0], RXPRTY[1:0] and RSOC. When TSEN is high, the active low receive read enable input, RRBENB controls when outputs RDAT[15:0], RXPRTY[1:0] and RSOC are driven. When TSEN is low, outputs RDAT[15:0], RXPRTY[1:0] and RSOC are always driven.
BUS8
Input
45
TSEN
Input
44
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TFCLK
Type Input
Pin No. 67
Function The transmit FIFO clock (TFCLK) is used to write words to the synchronous FIFO interface. TFCLK must cycle at a 52 MHz or lower instantaneous rate. TWRENB, TSOC, TXPRTY[1:0] and TDAT[15:0] are sampled on the rising edge of TFCLK. In addition, TCA is updated on the rising edge of TFCLK. The active low transmit write enable input (TWRENB) is used to initiate writes to the transmit FIFO. When sampled low using the rising edge of TFCLK, the 16-bit word on TDAT[15:0] is written into the transmit FIFO. When sampled high using the rising edge of TFCLK, no write is performed. A complete 53 octet cell must be written to the FIFO before it is inserted into the STS-3c/1 (STM1) SPE. Idle/unassigned cells are inserted when a complete cell is not available.
TWRENB
Input
68
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] TXPRTY[0] TXPRTY[1]
Type Input
Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 62 63 64
Function The transmit cell data (TDAT[15:0]) bus carries the ATM cell octets that are written to the transmit FIFO. When the 16-bit SCI-PHY interface is selected, (BUS8 is tied low), TDAT[15:0] contains the 16-bit wide word bus. When the 8-bit SCIPHY interface is selected (BUS8 is tied high), TDAT[7:0] contains the 8-bit wide word bus (TDAT[15:8] is not used). TDAT[15:0] is sampled on the rising edge of TFCLK and is considered valid only when TWRENB is simultaneously asserted.
Input
65 66
The transmit parity (TXPRTY[1:0]) signals indicate the parity of the TDAT[15:0] bus. TXPRTY[1] is expected to be the parity calculation over the TDAT[15:8] bus. TXPRTY[0] is expected to be the parity calculation over the TDAT[7:0] bus. Alternately, the device can be configured so that TXPRTY[1] is expected to be the parity calculation over the entire TDAT[15:0] bus. TXPRTY[0] should be tied low in this case. Odd or even parity selection can be made using the TACP FIFO Control register. TXPRTY[1:0] is sampled on the rising edge of TFCLK and is considered valid only when TWRENB is simultaneously asserted.
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TSOC
Type Input
Pin No. 69
Function The transmit start of cell (TSOC) signal marks the start of cell on the TDAT[15:0] bus. When TSOC is high, the first word of the cell structure is present on the TDAT[15:0] bus. It is not necessary for TSOC to be present at each cell. An interrupt may be generated if TSOC is high during any word other than the first word of the cell structure. TSOC is sampled on the rising edge of TFCLK and is considered valid only when TWRENB is simultaneously asserted. The transmit cell available (TCA) signal indicates when a cell is available in the transmit FIFO. When asserted, TCA indicates that the transmit FIFO is not full. When TCA is deasserted, it indicates that either the transmit FIFO is near full and can accept no more than four writes or that the transmit FIFO is full (as selected in the TACP FIFO Control register) In addition, to reduce FIFO latency, the FIFO full level can be programmed in the TACP FIFO Control register. The default state of TCA can be selected in the S/UNI-PLUS Master Control register. TCA is updated on the rising edge of TFCLK. The active polarity of this signal is programmable and defaults to active high. The transmit off (XOFF) input prevents the insertion of cells from the transmit FIFO. If XOFF is set high, the next cell transmitted is an idle/unassigned cell regardless of the number of cells in the FIFO. Idle/unassigned cells are transmitted until XOFF is deasserted. XOFF may be treated as an asynchronous signal. XOFF must be tied low if it is not used.
TCA
Output
70
XOFF
Input
71
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RTOH
Type Output
Pin No. 168
Function The receive transport overhead output (RTOH) contains the receive transport overhead bytes (A1, A2, J0/Z0, B1, E1, F1, D1-D3, H1-H3, B2, K1, K2, D4-D12, S1/Z1, M0 or M1/Z2, and E2) extracted from the receive stream. RTOH is updated on the falling edge of RTOHCLK. The receive transport overhead clock (RTOHCLK) is nominally a 5.184 MHz clock (STM-1/STS-3c) or a 1.728 MHz clock (STS-1) which provides timing to process the extracted receive transport overhead. When STS-3c (STM-1) mode is selected, RTOHCLK is a gapped 6.48 MHz clock. When STS-1 mode is selected, RTOHCLK is a gapped 2.16 MHz clock. RTOHCLK is updated on the falling edge of GROCLK. The receive transport overhead frame position (RTOHFP) signal is used to locate the individual receive transport overhead bits in the transport overhead output, RTOH. RTOHFP is set high while bit 1 (the most significant bit) of the first framing byte (A1) is present in the RTOH stream. RTOHFP is updated on the falling edge of RTOHCLK. The receive path overhead data (RPOH) signal contains the path overhead bytes (J1, B3, C2, G1, F2, H4, Z3, Z4, and Z5) extracted from the received STS-3c/1 frame. RPOH is updated on the falling edge of RPOHCLK. The receive path overhead clock (RPOHCLK) is nominally a 576 kHz clock which provides timing to process the extracted receive path overhead. RPOHCLK is a gapped 648 KHz clock. RPOHCLK is updated on the falling edge of GROCLK.
RTOHCLK
Output
164
RTOHFP
Output
167
RPOH
Output
171
RPOHCLK
Output
169
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RPOHFP
Type Output
Pin No. 170
Function The receive path overhead frame position (RPOHFP) signal may be used to locate the individual receive path overhead bits in the path overhead data stream, RPOH. RPOHFP is logic one while bit 1 (the most significant bit) of the path trace byte (J1) is present in the RPOH stream. RPOHFP is updated on the falling edge of RPOHCLK. The receive section DCC clock (RSDCLK) is a 192 kHz clock used to update the RSD output. RSDCLK is generated by gapping a 216 kHz clock. The receive section DCC (RSD) signal contains the serial section data communications channel (D1, D2, D3) extracted from the receive stream. RSD is updated on the falling edge of RSDCLK. The receive line DCC clock (RLDCLK) is a 576 kHz clock used to update the RLD output. RLDCLK is generated by gapping a 2.16 MHz clock. The receive line DCC (RLD) signal contains the serial line data communications channel (D4 D12) extracted from the receive stream. RLD is updated on the falling edge of RLDCLK. The receive orderwire clock (ROWCLK) is a 64 kHz clock used to update the RSOW, RSUC, and RLOW outputs. ROWCLK is generated by gapping a 72 kHz clock. The receive section orderwire (RSOW) signal contains the section orderwire channel (E1) extracted from the receive stream. RSOW is updated on the falling edge of ROWCLK.
RSDCLK
Output
156
RSD
Output
157
RLDCLK
Output
158
RLD
Output
159
ROWCLK
Output
155
RSOW
Output
163
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RSUC
Type Output
Pin No. 162
Function The receive section user channel (RSUC) signal contains the section user channel (F1) extracted from the receive stream. RSUC is updated on the falling edge of ROWCLK. The receive line orderwire (RLOW) signal contains the line orderwire channel (E2) extracted from the receive stream. RLOW is updated on the falling edge of ROWCLK. The receive overhead frame pulse (ROHFP) signal identifies the start of a byte on outputs RSOW, RSUC and RLOW. If required, ROHFP is one GROCLK clock cycle wide and can be used as a reset pulse for an external counter. Please refer to the functional timing diagrams for details. The transmit transport overhead input (TTOH) contains the transport overhead bytes (A1, A2, J0/Z0, E1, F1, D1-D3, H3, K1, K2, D4-D12, S1/Z1, M0 or M1/Z2, and E2) and error masks (H1, H2, B1, and B2) which may be inserted, or used to insert bit interleaved parity errors or payload pointer bit errors into the overhead byte positions in the transmit stream. Insertion is controlled by the TTOHEN input. TTOH is sampled on the rising edge of TTOHCLK.
RLOW
Output
154
ROHFP
Output
172
TTOH
Input
89
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TTOHEN
Type Input
Pin No. 91
Function The transmit transport overhead insert enable (TTOHEN) signal, together with internal register bits, controls the source of the transport overhead data which is transmitted. While TTOHEN is high, values sampled on the TTOH input are inserted into the corresponding transport overhead bit position (for the A1, A2, J0/Z0, E1, F1, D1-D3, K1, K2, H3, D4-D12, S1/Z1, M0 or M1/Z2, and E2 bytes). While TTOHEN is low, default values are inserted into these transport overhead bit positions. A high level on TTOHEN during the B1, B2 or H1-H2 bit positions enables an error mask. While the error mask is enabled, a high level on input TTOH causes the corresponding B1, B2 or H1-H2 bit position to be inverted. A low level on TTOH allows the corresponding bit position to pass through the S/UNI-PLUS uncorrupted. TTOHEN is sampled on the rising edge of TTOHCLK. The transmit transport overhead clock (TTOHCLK) is nominally a 5.184 MHz clock (STS-3c/STM-1) or a 1.728 MHz clock (STS-1) clock which provides timing for circuitry that sources the transport overhead stream, TTOH. When STS-3c (STM-1) mode is selected, TTOHCLK is a gapped 6.48 MHz clock. When STS-1 mode is selected, TTOHCLK is a gapped 2.16 MHz clock. TTOHCLK is updated in the rising edge of GTOCLK. The transmit transport overhead frame position (TTOHFP) signal is used to locate the individual transport overhead bits in the transport overhead input, TTOH. TTOHFP is set high while bit 1 (the most significant bit) of the first framing byte (A1) is expected on TTOH. TTOHFP is updated on the falling edge of TTOHCLK.
TTOHCLK
Output
92
TTOHFP
Output
90
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DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TPOH
Type Input
Pin No. 85
Function The transmit path overhead data (TPOH) signal contains the path overhead bytes (J1, C2, G1, F2, H4, Z3, Z4, and Z5) and error masks (B3) which may be inserted, or used to insert path BIP-8 errors into the path overhead byte positions in the transmit stream. Insertion is controlled by the TPOHEN input, or by bits in internal registers. TPOH is sampled on the rising edge of TPOHCLK. The transmit path overhead insert enable (TPOHEN) signal, together with internal register bits, controls the source of the path overhead data which is transmitted. While TPOHEN is high, values sampled on the TPOH input are inserted into the corresponding path overhead bit position (for the J1, C2, G1, H4, F2, Z3, Z4, and Z5 bytes). While TPOHEN is low, values obtained from internal registers are inserted into these path overhead bit positions. A high level on TPOHEN during the B3 bit positions enables an error mask. While the error mask is enabled, a high level on input TPOH causes the corresponding B3 bit position to be inverted. A low level on TPOH allows the corresponding bit position to pass through the S/UNI-PLUS uncorrupted. TPOHEN is sampled on the rising edge of TPOHCLK. The transmit path overhead clock (TPOHCLK) is nominally a 576 kHz clock which provides timing for circuitry that sources the path overhead stream, TPOH. TPOHCLK is a gapped 810 KHz clock. TPOHCLK is updated in the falling edge of GTOCLK.
TPOHEN
Input
87
TPOHCLK
Output
88
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TPOHFP
Type Output
Pin No. 86
Function The transmit path overhead frame position (TPOHFP) signal may be used to locate the individual path overhead bits in the path overhead data stream, TPOH. TPOHFP is logic one while bit 1 (the most significant bit) of the path trace byte (J1) is expected in the TPOH stream. TPOHFP is updated on the falling edge of TPOHCLK. The transmit orderwire clock (TOWCLK) is a 64 kHz clock used to sample the TSOW, TSUC, and TLOW inputs. TOWCLK is generated by gapping a 72 kHz clock. The transmit section orderwire (TSOW) signal contains the section orderwire channel (E1) inserted into the transmit stream. When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH and TTOHEN takes precedence over overhead sourced using TSOW. TSOW is sampled on the rising edge of TOWCLK. The transmit section user channel (TSUC) signal contains the section user channel (F1) inserted into the transmit stream. When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH and TTOHEN takes precedence over overhead sourced using TSUC. TSUC is sampled on the rising edge of TOWCLK. The transmit line orderwire (TLOW) signal contains the line orderwire channel (E2) inserted into the transmit stream. When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH and TTOHEN takes precedence over overhead sourced using TLOW. TLOW is updated on the rising edge of TOWCLK.
TOWCLK
Output
96
TSOW
Input
93
TSUC
Input
94
TLOW
Input
95
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TSDCLK
Type Output
Pin No. 104
Function The transmit section DCC clock (TSDCLK) is a 192 kHz clock used to sample the TSD input. TSDCLK is generated by gapping a 216 kHz clock. The transmit section DCC (TSD) signal contains the serial section data communications channel (D1, D2, D3). When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH and TTOHEN takes precedence over overhead sourced using TSD. TSD is sampled on the rising edge of TSDCLK. The transmit line DCC clock (TLDCLK) is a 576 kHz clock used to sample the TLD input. TLDCLK is generated by gapping a 2.16 MHz clock. The transmit line DCC (TLD) signal contains the serial line data communications channel (D4 D12). When not used, this input should be connected to logic zero. Overhead sourced using inputs TTOH and TTOHEN takes precedence over overhead sourced using TLD. TLD is sampled on the rising edge of TLDCLK. The receive cell pulse (RCP) signal marks the most significant bit (MSB) of a cell header's GFC field on output, RGFC. RCP is updated on the falling edge of GROCLK. The receive generic flow control (RGFC) signal contains the serialized GFC field extracted from receive cells. The GFC field is output MSB first. The RCP output can be used to identify the MSB bit of every GFC field. The GFC Control register can be used to gate off individual GFC bits. RGFC is updated on the falling edge of GROCLK.
TSD
Input
103
TLDCLK
Output
102
TLD
Input
101
RCP
Output
174
RGFC
Output
173
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TCP
Type Output
Pin No. 77
Function The transmit cell pulse (TCP) signal is provided to locate the most significant GFC bit (GFC[3]) of a cell's GFC field sourced on input TGFC. TCP pulses high for one SPECLK period to identify the SPECLK cycle before the cycle the GFC[3] bit is output on TGFC. TCP is updated on the falling edge of GTOCLK. The transmit generic flow control (TGFC) input contains GFC bits that can be inserted into the GFC fields of transmitted cells (including idle/unassigned cells). Insertion is controlled using bits in the TACP Fixed Stuff/GFC register. TGFC is sampled on the rising edge of GTOCLK. The parallel output port (POP[3:0]) is used to control the operation of PMD devices. The signal levels on this parallel output port correspond to the bit values contained in the S/UNI-PLUS Parallel I/O Port Register. The parallel input port (PIP[3:0]) is used to monitor the operation of PMD devices. An interrupt may be generated when state changes are detected on the monitored signals. The realtime signal levels on this port are available in the S/UNI-PLUS Parallel I/O Port register. Each of the inputs contains an internal pull-down resistor. The active low chip select (CSB) signal is low during S/UNI-PLUS register accesses. Note when not being used, CSB should be tied high. If CSB is not required (i.e. register accesses controlled using the RDB and WRB signals only), CSB should be connected to an inverted version of the RSTB input.
TGFC
Input
78
POP[3] POP[2] POP[1] POP[0] PIP[3] PIP[2] PIP[1] PIP[0]
Output
105 106 107 108
Input
109 110 111 112
CSB
Input
22
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RDB
Type Input
Pin No. 24
Function The active low read enable (RDB) signal is low during S/UNI-PLUS register read accesses. The S/UNI-PLUS drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are low. The active low write strobe (WRB) signal is low during a S/UNI-PLUS register write accesses. The D[7:0] bus contents are clocked into the addressed register on the rising WRB edge while CSB is low. The bidirectional data bus D[7:0] is used during S/UNI-PLUS register read and write accesses.
WRB
Input
23
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7]/TRS
I/O
27 28 31 32 35 36 39 40
Input
12 13 14 15 16 17 18 19
The address bus A[7:0] selects specific registers during S/UNI-PLUS register accesses.
The test register select (TRS) signal selects between normal and test mode register accesses. TRS is high during test mode register accesses, and is low during normal mode register accesses.
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RSTB
Type Input
Pin No. 21
Function The active low reset (RSTB) signal provides an asynchronous S/UNI-PLUS reset. RSTB is a Schmitt triggered input with an integral pull up resistor. The address latch enable (ALE) is active high and latches the address bus A[7:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-PLUS to interface to a multiplexed address/data bus. ALE has an integral pull up resistor. The active low interrupt (INTB) signal goes low when a S/UNI-PLUS interrupt source is active, and that source is unmasked. The S/UNI-PLUS may be enabled to report many alarms or events via interrupts. Examples are loss of signal (LOS), loss of frame (LOF), line AIS, line remote defect indication (LRDI), loss of pointer (LOP), path AIS, path RDI, and many others. INTB returns high when the interrupt is acknowledged via an appropriate register access. INTB is an open drain output. The test clock (TCK) signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port. The test mode select (TMS) signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. The test data input (TDI) signal carries test data into the S/UNI-PLUS via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor.
ALE
Input
20
INTB
Output
25
TCK
Input
46
TMS
Input
43
TDI
Input
42
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TDO
Type Tristate
Pin No. 41
Function The test data output (TDO) signal carries test data out of the S/UNI-PLUS via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is tristate except when scanning of data is in progress. The active low test reset (TRSTB) signal provides an asynchronous S/UNI-PLUS test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. TRSTB must be asserted during the power up sequence. Note that when not being used, TRSTB must be connected to the RSTB input.
TRSTB
Input
26
VDD_DC1 VDD_DC2 VDD_DC3 VDD_DC4 VDD_DC5 VDD_DC6 VDD_DC7 VDD_DC8 VDD_DC9 VDD_DC10 VDD_DC11
Power
7 29 37 60 80 98 129 160 177 197 206
The DC power (VDD_DC1 - VDD_DC11) pins should be connected to a well decoupled +5 V DC in common with VDD_AC.
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name VSS_DC1 VSS_DC2 VSS_DC3 VSS_DC4 VSS_DC5 VSS_DC6 VSS_DC7 VSS_DC8 VSS_DC9 VSS_DC10 VSS_DC11 VDD_AC1 VDD_AC2 VDD_AC3 VDD_AC4 VDD_AC5 VDD_AC6 VDD_AC7 VDD_AC8 VSS_AC1 VSS_AC2 VSS_AC3 VSS_AC4 VSS_AC5 VSS_AC6 VSS_AC7 VSS_AC8
Type Ground
Pin No. 8 30 38 61 79 99 130 161 178 198 207
Function The DC ground (VSS_DC1 - VSS_DC11) pins should be connected to GND in common with VSS_AC.
Power
4 33 82 97 133 165 183 200
The pad ring power (VDD_AC1 - VDD_AC8) pins should be connected to a well decoupled +5 V DC in common with VDD_DC
Ground
5 34 83 100 134 166 184 201
The pad ring ground (VSS_AC1 - VSS_AC8) pins should be connected to GND in common with VSS_DC.
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name TAVD1
Type Power
Pin No. 115
Function The power (TAVD1) pin for the transmit clock synthesizer reference circuitry. TAVD1 should be connected to a clean, well decoupled, +5V supply. The ground (TAVS1) pin for the transmit clock synthesizer reference circuitry. TAVS1 should be connected to a clean ground reference. The power (TAVD2) pin for the transmit clock synthesizer oscillator. TAVD2 should be connected to a clean, well decoupled, +5V supply. The ground (TAVS2) pin for the transmit clock synthesizer oscillator. TAVS2 should be connected to a clean ground reference. The power (TAVD3) pin for the transmit reference clock (TRCLK+/-) inputs. TAVD3 should be connected to a clean, well decoupled, +5V supply. The ground (TAVS3) pin for the transmit reference clock (TRCLK+/-) inputs. TAVS3 should be connected to a clean ground reference. The transmit pad power (TXVDD) supplies the TXC+/- and TXD+/- outputs. TXVDD is physically isolated from the other device power pins and should be a clean, well decoupled +5 V supply to minimize the noise coupled into the transmit stream. The transmit pad ground (TXVSS) is the return path for the TXC+/- and TXD+/- outputs. TXVSS is physically isolated from the other device ground pins and should be clean to minimize the noise coupled into the transmit stream. The power (RAVD1) pin for receive clock and data recovery block reference circuitry. RAVD1 should be connected to a clean, well decoupled, +5V supply.
TAVS1
Ground
116
TAVD2
Power
117
TAVS2
Ground
118
TAVD3
Power
119
TAVS3
Ground
122
TXVDD
Power
123
TXVSS
Ground
128
RAVD1
Power
147
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PM5347 S/UNI-PLUS
DATA SHEET PMC-941033 ISSUE 6 SATURN USER NETWORK INTERFACE PLUS
Pin Name RAVS1
Type Ground
Pin No. 148
Function The ground (RAVS1) pin for receive clock and data recovery block reference circuitry. RAVS1 should be connected to a clean ground reference. The power (RAVD2) pin for receive clock and data recovery block active loop filter and oscillator. RAVD2 should be connected to a clean, well decoupled, +5V supply. The ground (RAVS2) pin for receive clock and data recovery block active loop filter and oscillator. RAVS2 should be connected to a clean ground reference. The power (RAVD3) pin for the RXD+/- and ALOS+/- PECL inputs. RAVD3 should be connected to a clean, well decoupled, +5V supply. The ground (RAVS3) pin for the RXD+/- and ALOS+/- PECL inputs. RAVS3 should be connected to a clean ground reference. The power (RAVD4) pin for the RRCLK+/- PECL inputs. RAVD4 should be connected to a clean, well decoupled, +5V supply.. The ground (RAVS4) pin for the RRCLK+/- PECL inputs. RAVS4 should be connected to a clean ground reference.
RAVD2
Power
145
RAVS2
Ground
146
RAVD3
Power
140
RAVS3
Ground
139
RAVD4
Power
141
RAVS4
Ground
144
Notes on Pin Description: 1. All S/UNI-PLUS inputs and bidirectionals present minimum capacitive loading and operate at TTL logic levels except for the RXD+/-, ALOS+/-, RRCLK+/-, and TRCLK+/- inputs which operate at pseudo-ECL (PECL) logic levels. 2. The TXD+/- and TXC+/- outputs have a 6 mA drive capability. The GTOCLK, GROCLK, RSOC, RDAT[15:0], RXPRTY[1:0], RCA, TCA and D[7:0] outputs and bidirectionals have a 4 mA drive capability. All other S/UNI-PLUS digital outputs and bidirectionals have 2 mA drive capability.
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3. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors. 4. The VSS_DC, VSS_AC, TXVSS, and AVS ground pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the S/UNI-PLUS. 5. The VDD_AC , VDD_AC, TXVDD, and AVD power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the S/UNI-PLUS. 6. The TAVD[3:1] and RAVD[4:1] pins provide power to sensitive analog circuitry in the S/UNI-PLUS. These signals should be connected to the PCB VDD power plane at a point where the supply is clean and as free as possible of digitally induced switching noise. In a typical system, TAVD and RAVD should be "starred" back to a clean reference point on the PCB, for example at the card edge connector where the system VDD enters the PCB. In some systems a clean VDD supply cannot be readily obtained, and RAVD and TAVD may require separate regulation. 7. Each TAVD and RAVD pin should be separately decoupled using ceramic decoupling capacitors located as close as possible to the S/UNI-PLUS. 8. The TAVS[3:1] and RAVS[4:1] pins provide the ground return path for sensitive analog circuitry in the S/UNI-PLUS. These signals should be connected to the PCB ground plane at a point where the ground is clean and as free as possible of digital return currents. In a typical system, TAVS and RAVS should be "starred" back to a clean reference point on the PCB, for example at the card edge connector where the system ground reference enters the PCB. 9. Do not exceed 100 mA of current on any pin during the power-up or powerdown sequence. 10. Before any input activity occurs, ensure that the device power supplies are within their nominal voltage range. 11. Hold the device in the reset condition until the device power supplies are within their nominal voltage range. 12. Ensure that all digital power is applied simultaneously, and it is applied before the analog power is applied.
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9 9.1
FUNCTIONAL DESCRIPTION Clock Recovery The clock recovery unit recovers the clock from the incoming bit serial data stream. The clock recovery unit is fully compliant with SONET and SDH jitter tolerance requirements. The clock recovery unit utilizes a low frequency reference clock to train and monitor its clock recovery PLL. Under loss of signal conditions, the clock recovery unit continues to output a line rate clock that is locked to this reference for keep alive purposes. The clock recovery unit can be configured to utilize reference clocks at 6.48 or 19.44 MHz. The clock recovery unit provides status bits that indicate whether it is locked to data or the reference. The clock recovery unit also supports diagnostic loopback and a loss of signal input that squelches normal input data. Initially, the PLL locks to the reference clock, RRCLK+/-. When the frequency of the recovered clock is within 488 ppm of the reference clock, the PLL attempts to lock to the data. Once in data lock, the PLL reverts to the reference clock if no data transitions occur in 80 bit periods or if the recovered clock drifts beyond 488 ppm of the reference clock. When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the transmit clock is directly related to the RRCLK+/- reference accuracy in the case of a loss of signal condition. To meet the Bellcore GR-253CORE SONET Network Element free-run accuracy specification, the reference must be within +/-20ppm. When not loop timed, the RRCLK+/- accuracy may be relaxed to +/-50ppm. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance which exceeds the minimum tolerance proposed for SONET equipment by GR253-CORE (Figure 3). The jitter tolerance illustrated is associated with the external loop filter components recommended in the Operation section.
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Figure 3
- STS-3c/STM-1 and STS-1 Jitter Tolerance
100
10
1
GR-253-CORE
0.1 10 100 1000 10000 100000 1000000 10000000
Jitter Frequency (Hz)
9.2
Serial to Parallel Converter The Serial to Parallel Converter (SIPO) converts the received bit serial stream to a byte serial stream. The SIPO searches for the SONET/SDH framing pattern (A1, A2) in the receive stream, and performs serial to parallel conversion on octet boundaries.
9.3
Receive Section Overhead Processor The Receive Section Overhead Processor (RSOP) provides frame synchronization, descrambling, section level alarm and performance monitoring. In addition, it extracts the section orderwire channel, the section user channel, the section data communication channel from the section overhead and provides it serially on outputs RSOW, RSUC and RSD respectively. Framer The Framer Block determines the in-frame/out-of-frame status of the receive stream.
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While in-frame, the framing bytes (A1, A2) in each frame are compared against the expected pattern. Out-of-frame is declared when four consecutive frames containing one or more framing pattern errors have been received. While out-of-frame, the SIPO block monitors the receive stream for an occurrence of the framing pattern. When a framing pattern has been recognized, the Framer block verifies that an error free framing pattern is present in the next frame before declaring in-frame. Descramble The Descramble Block utilizes a frame synchronous descrambler to process the receive stream. The generating polynomial is x7 + x6 + 1 and the sequence length is 127. Details of the descrambling operation are provided in the references. Note that the framing bytes (A1 and A2) and the trace/growth bytes (J0/Z0) are not descrambled. A register bit is provided to disable the descrambling operation. Error Monitor The Error Monitor Block calculates the received section BIP-8 error detection code (B1) based on the scrambled data of the complete STS-3c/1 (STM-1) frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 code is compared with the BIP-8 code extracted from the B1 byte of the following frame. Differences indicate that a section level bit error has occurred. Up to 64000 (8 x 8000) bit errors can be detected per second. The Error Monitor Block accumulates these section level bit errors in a 16-bit saturating counter that can be read via the microprocessor interface. Circuitry is provided to latch this counter so that its value can be read while simultaneously resetting the internal counter to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that this counter be polled at least once per second so as not to miss bit error events. Loss of Signal The Loss of Signal Block monitors the scrambled data of the receive stream for the absence of 1's. When 20 3 s of all zeros patterns is detected, a loss of signal (LOS) is declared. Loss of signal is cleared when two valid framing words are detected and during the intervening time, no loss of signal condition is detected. LOS is updated on the falling edge of GROCLK.
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Loss of Frame The Loss of Frame Block monitors the in-frame / out-of-frame status of the Framer Block. A loss of frame (LOF) is declared when an out-of-frame condition persists for 3 ms. The LOF is cleared when an in-frame condition persists for a period of 3 ms. To provide for intermittent out-of-frame (or in-frame) conditions, the 3 ms timer is not reset to zero until an in-frame (or out-of-frame) condition persists for 3 ms. LOF is updated on the falling edge of GROCLK. 9.4 Receive Line Overhead Processor The Receive Line Overhead Processor (RLOP) provides line level alarm and performance monitoring. In addition, it extracts the line orderwire channel and the line data communication channel from the line overhead and provides it serially on outputs RLOW and RLD respectively. Line RDI Detect The Line RDI Detect Block detects the presence of Line Remote Defect Indication (LRDI) in the receive stream. Output LRDI is asserted when a 110 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. LRDI is removed when any pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. LRDI is updated on the falling edge of GROCLK. Line AIS Detect The Line AIS Block detects the presence of a Line Alarm Indication Signal (LAIS) in the receive stream. Output LAIS is asserted when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte, for three or five consecutive frames. LAIS is removed when any pattern other than 111 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. LAIS is updated with on the falling edge of GROCLK. Automatic Protection Switch Control Block The Automatic Protection Switch Control (APSC) Block filters and captures the receive automatic protection switch channel bytes (K1 and K2) allowing them to be read via the S/UNI-PLUS Receive K1 Register and the S/UNI-PLUS Receive K2 Register. The bytes are filtered for three frames before being written to these registers. A protection switching byte failure alarm is declared when twelve
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successive frames have been received, where no three consecutive frames contain identical K1 bytes. The protection switching byte failure alarm is removed upon detection of three consecutive frames containing identical K1 bytes. The detection of invalid APS codes is done in software by polling the S/UNI-PLUS Receive K1 Register and the S/UNI-PLUS Receive K2 Register. Error Monitor The Error Monitor Block calculates the received line BIP-8/24 error detection code (B2) based on the line overhead and synchronous payload envelope of the receive stream. The line BIP code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP code is compared with the BIP code extracted from the B2 bytes of the following frame. Any differences indicate that a line layer bit error has occurred. Up to 192000 (24 x 8000) bit errors can be detected per second. The Error Monitor Block accumulates these line layer bit errors in a 20 bit saturating counter that can be read via the microprocessor interface. During a read, the counter value is latched and the counter is reset to 0 (or 1, if there is an outstanding event). Note, this counter should be polled at least once per second to avoid saturation which in turn may result in missed bit error events. The Error Monitor Block also accumulates line far end block error indications (contained in the M0 or M1 byte) in a similar manner. 9.5 Transport Overhead Extract Port The Transport Overhead Extract Port extracts the entire receive transport overhead on RTOH for optional external TOH processing. RTOHFP is provided to identify the most significant bit of the A1 framing byte on RTOH. The transport overhead clock, RTOHCLK is nominally a 5.184 MHz (STS-3c/STM-1 mode) or a 1.728 MHz (STS-1 mode) clock. RTOH and RTOHFP are updated on the falling edge of RTOHCLK. 9.6 Receive Path Overhead Processor The Receive Path Overhead Processor (RPOP) provides pointer interpretation, extraction of path overhead, extraction of the synchronous payload envelope, and path level alarm indication and performance monitoring.
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Pointer Interpreter The Pointer Interpreter Block interprets the incoming pointer (H1, H2) as specified in the references. The pointer value is used to determine the location of the path overhead in the receive stream. The algorithm can be modeled by a finite state machine. Within the pointer interpretation algorithm, three states are defined as shown in Figure 4: NORM_state (NORM) AIS_state (AIS) LOP_state (LOP) The transition between states will be consecutive events (indications), e.g., three consecutive AIS indications to go from the NORM_state to the AIS_state. The kind and number of consecutive indications activating a transition is chosen such that the behavior is stable and insensitive to low BER. The only transition on a single event is the one from the AIS_state to the NORM_state after receiving a NDF enabled with a valid pointer value. It should be noted that, since the algorithm only contains transitions based on consecutive indications, this implies that, for example, non-consecutively received invalid indications do not activate the transitions to the LOP_state. The following events (indications) are defined: norm_point : NDF_enable: AIS_ind: inc_ind: disabled NDF + ss + offset value equal to active offset enabled NDF + ss + offset value in range of 0 to 782 H1 = 'hFF, H2 = 'hFF disabled NDF + ss + majority of I bits inverted + no majority of D bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago disabled NDF + ss + majority of D bits inverted + no majority of I bits inverted + previous NDF_enable, inc_ind or dec_ind more than 3 frames ago not any of above (i.e., not norm_point, and not NDF_enable, and not AIS_ind, and not inc_ind and not dec_ind)
dec_ind:
inv_point:
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new_point: Notes:
disabled_NDF + ss + offset value in range of 0 to 782 but not equal to active offset.
1. Active offset is defined as the accepted current phase of the SPE in the NORM_state and is undefined in the other states. 2. Enabled new data flag (NDF) is defined as the following bit patterns: 1001, 0001, 1101, 1011, 1000. 3. Disabled NDF is defined as the following bit patterns: 0110, 1110, 0010, 0100, 0111. 4. The remaining six NDF codes (0000, 0011, 0101, 1010, 1100, 1111) result in an inv_point indication. 5. Ss bits are unspecified in SONET and has bit pattern 10 in SDH 6. The use of ss bits in definition of indications may be optionally disabled. 7. The requirement for previous NDF_enable, inc_ind or dec_ind be more than 3 frames ago may be optionally disabled. 8. New_point is also an inv_point.
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Figure 4
- Pointer Interpretation State Diagram
3 x eq_new _po int inc_in d / dec _ind N D F _enab le
NORM
eq 3x _n
ND
8x in v _ po int
b le
ew
F_
8x ND F _e na
nt
_ A IS 3x
_p
en
po i
o in
ab
3x e q_ n ew _
t
le
in d
3 x A IS _ind
LO P
A IS
8 x inv_point
The transitions indicated in the state diagram are defined as follows: * * * * * inc_ind/dec_ind: offset adjustment (increment or decrement indication) 3 x eq_new_point: NDF_enable: 3 x AIS_ind: 8 x inv_point: three consecutive equal new_point indications single NDF_enable indication three consecutive AIS indications eight consecutive inv_point indications
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*
8 x NDF_enable eight consecutive NDF_enable indications
Notes: 1. The transitions from NORM_state to NORM_state do not represent state changes but imply offset changes. 2. 3 x new_point takes precedence over 8 x inv_point. 3. All three offset values received in 3 x eq_new_point must be identical. 4. "Consecutive event counters" are reset to zero on a change of state. The Pointer Interpreter Block detects loss of pointer (LOP) in the receive stream. LOP is declared (LOP output set high) on entry to the LOP_state as a result of eight consecutive invalid pointers or eight consecutive new data flag (NDF) enabled indications. LOP is removed (LOP output set low) when the same valid pointer with normal NDF is detected for three consecutive frames. Incoming STS Path AIS (pointer bytes set to all ones) does not cause entry into the LOP state. The Pointer Interpreter Block detects path AIS in the receive stream. PAIS is declared (PAIS output set high) on entry to the AIS_state after three consecutive AIS indications. PAIS is removed (PAIS set low) when the same valid pointer with normal NDF is detected for three consecutive frames or when a valid pointer with NDF enabled is detected. Invalid pointer indications (inv_point), invalid NDF codes, new pointer indications (new_point), discontinuous change of pointer alignment, and illegal pointer changes are also detected and reported by the Pointer Interpreter block via register bits. An invalid NDF code is any NDF code that does not match the NDF enabled or NDF disabled definitions. The third occurrence of equal new_point indications (3 x eq_new_point) is reported as a discontinuous change of pointer alignment event (DISCOPA) instead of a new pointer event and the active offset is updated with the receive pointer value. An illegal pointer change is defined as a inc_ind or dec_ind indication that occurs within three frames of the previous inc_ind, dec_ind or NDF_enable indications. Illegal pointer changes may be optionally disabled via register bits. The pointer value is used to extract the path overhead from the receive stream. The current pointer value can be read from an internal register.
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SPE Timing The SPE Timing Block provides SPE timing information to the Error Monitor and the Extract blocks. The block contains a free running timeslot counter that is initialized by a J1 byte identifier (which identifies the first byte of the SPE). Control signals are provided to the Error Monitor and the Extract blocks to identify the Path Overhead bytes and to downstream circuitry to extract the ATM cell payload. Error Monitor The Error Monitor Block contains two 16-bit counters that are used to accumulate path BIP-8 errors (B3), and far end block errors (FEBEs). The contents of the two counters may be transferred to holding registers, and the counters reset under microprocessor control. Path BIP-8 errors are detected by comparing the path BIP-8 byte (B3) extracted from the current frame, to the path BIP-8 computed for the previous frame. FEBEs are detected by extracting the 4-bit FEBE field from the path status byte (G1). The legal range for the 4-bit field is between 0000 and 1000, representing zero to eight errors. Any other value is interpreted as zero errors. Path Remote Defect Indication (PRDI) and auxiliary PRDI (APRDI) are detected by extracting bit 5 and bit 6 of the path status byte. PRDI (APRDI) is declared when bit 5 (bit 6) is high for five or ten consecutive frames. PRDI (APRDI) is removed when bit 5 (bit 6) is low for five or ten consecutive frames. 9.7 Path Overhead Extract The Path Overhead Extract Block extracts and serializes the receive path overhead bytes on RPOH. Output RPOHFP is provided to identify the most significant bit of the path trace byte (J1) on RPOH. The path overhead clock, RPOHCLK is nominally a 576 kHz clock. RPOH and RPOHFP are updated on the falling edge of RPOHCLK. 9.8 Receive ATM Cell Processor The Receive ATM Cell Processor (RACP) performs ATM cell delineation, provides cell filtering based on idle/unassigned cell detection and HCS error detection, and performs ATM cell payload descrambling. The RACP also
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provides a four cell deep receive FIFO. This FIFO is used to separate the STS-3c/1 (STM-1) line timing from the higher layer ATM system timing. Cell Delineation Cell Delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the cell header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. Cells are assumed to be byte-aligned to the synchronous payload envelope. The cell delineation algorithm searches the 53 possible cell boundary candidates individually to determine the valid cell boundary location. While searching for the cell boundary location, the cell delineation circuit is in the HUNT state. When a correct HCS is found, the cell delineation state machine locks on the particular cell boundary, corresponding to the correct HCS, and enters the PRESYNC state. The PRESYNC state validates the cell boundary location. If the cell boundary is invalid, an incorrect HCS will be received within the next DELTA cells, at which time a transition back to the HUNT state is executed. If no HCS errors are detected in this PRESYNC period, the SYNC state is entered. While in the SYNC state, synchronization is maintained until ALPHA consecutive incorrect HCS patterns are detected. In such an event a transition is made back to the HUNT state. The state diagram of the delineation process is shown in Figure 5.
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Figure 5
- Cell Delineation State Diagram
correct HCS (byte by byte)
HUNT
Incorrect HCS (cell by cell)
PRESYNC
ALPHA consecutive incorrect HCS's (cell by cell)
SYNC
DELTA consecutive correct HCS's (cell by cell)
The values of ALPHA and DELTA determine the robustness of the delineation process. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6. These values result in an average time to delineation of 100.98 s and 33.66 s for the STS-1 and STS-3c rates, respectively. Descrambler The self synchronous descrambler operates on the 48 byte cell payload only. The circuitry descrambles the information field using the x43 + 1 polynomial. The descrambler is disabled for the duration of the header and HCS fields and may optionally be disabled for the payload. Cell Filter and HCS Verification Cells are filtered (or dropped) based on HCS errors and/or a cell header pattern. Cell filtering is optional and is enabled through the RACP registers. Cells are passed to the receive FIFO while the cell delineation state machine is in the
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SYNC state as described above. When both filtering and HCS checking are enabled, cells are dropped if uncorrectable HCS errors are detected, or if the corrected header contents match the pattern contained in the RACP Match Header Pattern and RACP Match Header Mask registers. Idle or unassigned cell filtering is accomplished by writing the appropriate cell header pattern into the RACP Match Header Pattern and RACP Match Header Mask registers. Idle/Unassigned cells are assumed to contain the all zeros pattern in the VCI and VPI fields. The RACP Match Header Pattern and RACP Match Header Mask registers allow filtering control over the contents of the GFC, PTI, and CLP fields of the header. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RACP block verifies the received HCS using the polynomial, x 8 + x2 + x + 1. The coset polynomial, x6 + x4 + x2 + 1, is added (modulo 2) to the received HCS octet before comparison with the calculated result. While the cell delineation state machine (described above) is in the SYNC state, the HCS verification circuit implements the state machine shown in Figure 6.
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Figure 6
- HCS Verification State Diagram
ATM DELINEATION SYNC STATE
ALPHA consecutive incorrect HCS's (To HUNT state)
Apparent Multi-Bit Error (Drop Cell) No Errors Detected (Pass Cell) CORRECTION MODE
Single-Bit Error (Correct Error and Pass Cell)
Errors Detected (Drop Cell)
DETECTION MODE
DELTA consecutive correct HCS's (From PRESYNC state)
No Errors Detected In M Cells (Pass Mth Cell) No Errors Detected (Pass Cell)
In normal operation, the HCS verification state machine remains in the 'Correction Mode' state. Incoming cells containing no HCS errors are passed to the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the state machine transitions to the 'Detection Mode' state. In this state, programmable HCS error filtering is provided. The detection of any HCS error causes the corresponding cell to be dropped. The state machine transitions back to the 'Correction Mode' state when M (where M = 1, 2, 4, 8) cells are received with correct HCSs. The Mth cell is not discarded. Performance Monitor The Performance Monitor consists of two 12-bit saturating HCS error event counters and a 21-bit saturating receive cell counter. One of the counters accumulates correctable HCS errors which are HCS single-bit errors detected
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and corrected while the HCS Verification state machine is in the 'Correction Mode' state. The second counter accumulates uncorrectable HCS errors which are HCS bit errors detected while the HCS Verification state machine is in the 'Detection Mode' state or HCS bit errors detected but not corrected while the state machine is in the 'Correction Mode' state. The 21-bit receive cell counter counts all cells written into the receive FIFO. Filtered cells are not counted. Each counter may be read through the microprocessor interface. Circuitry is provided to latch these counters so that their values can be read while simultaneously resetting the internal counters to 0 or 1, if appropriate, so that a new period of accumulation can begin without loss of any events. It is intended that the counter be polled at least once per second so as not to miss HCS error events. GFC Extraction Port The GFC Extraction Port outputs the received GFC bits in a serial stream. The four GFC bits are presented for each received cell, with the RCP output indicating the position of the most significant bit. The updating of RGFC by particular GFC bits may be disabled through an internal register. The serial link is forced low if cell delineation is lost. Receive FIFO The Receive FIFO provides FIFO management and the asynchronous interface between the S/UNI-PLUS device and the external environment. The receive FIFO can accommodate four cells. The receive FIFO provides for the separation of the STS-3c/1 (STM-1) line or physical layer timing from the ATM layer timing. The FIFO supports two data structures. The first data structure consists of twenty-seven 16-bit words comprising the five octet cell header, a cell header status octet and the forty-eight octet payload. The second data structure consists of fifty three 8-bit words comprising the five octet cell header and the forty-eight octet payload. Refer to the Operation section for more detail on these data structures. Management functions include filling the receive FIFO, indicating when cells are available to be read from the receive FIFO, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun and underrun conditions. Upon detection of an overrun, the FIFO is automatically reset. Up to four cells may be lost during the FIFO reset operation. Upon detection of an underrun, the offending read is ignored. FIFO overruns are indicated through a maskable
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interrupt and register bit. The FIFO interface provided to the system is a synchronous interface emulating commercial synchronous FIFOs. All receive FIFO signals, RSOC, RRDENB, RCA, RXPRTY[1:0] and RDAT[15:0] are either sampled or updated on the rising edge of the RFCLK clock input. 9.9 Clock Synthesis The transmit clock may be synthesized from a 19.44 MHz or 6.48 MHz reference. The transfer function yields a typical low pass corner of 500 kHz with a 19.44 MHz reference and 170 kHz with a 6.48 MHz reference, above which reference jitter is attenuated at 12dB per octave. The design of the loop filter and PLL is optimized for minimum intrinsic jitter. With a jitter free 19.44 MHz reference, the intrinsic jitter is typically less than 0.01 UI RMS when measured using a high pass filter with a 12 kHz cutoff frequency. The TRCLK+/- reference should be within 20 ppm to meet the SONET free-run accuracy requirements specified in GR-253-CORE. 9.10 Parallel to Serial Converter The Parallel to Serial Converter (PISO) converts the transmit byte serial stream to a bit serial stream. 9.11 Transmit Section Overhead Processor The Transmit Section Overhead Processor (TSOP) provides frame pattern insertion (A1, A2), scrambling, section level alarm signal insertion, and section BIP-8 (B1) insertion. Line AIS Insert Line AIS insertion results in all bits of the SONET/SDH frame being set to 1 before scrambling except for the section overhead. The Line AIS Insert Block substitutes all ones as described when enabled by the TLAIS input or through an internal register accessed through the microprocessor interface. Activation or deactivation of line AIS insertion is synchronized to frame boundaries. BIP-8 Insert The BIP-8 Insert Block calculates and inserts the BIP-8 error detection code (B1) into the transmit stream.
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The BIP-8 calculation is based on the scrambled data of the complete STS-3c/1 (STM-1) frame. The section BIP-8 code is based on a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-8 code is then inserted into the B1 byte of the following frame before scrambling. BIP-8 errors may be continuously inserted under register control for diagnostic purposes. Framing and Identity Insert The Framing and Identity Insert Block inserts the framing bytes (A1, A2) and trace/growth bytes (J0/Z0) into the STS-3c/1 (STM-1) frame. Framing bit errors may be continuously inserted under register control for diagnostic purposes. Scrambler The Scrambler Block utilizes a frame synchronous scrambler to process the transmit stream when enabled through an internal register accessed via the microprocessor interface. The generating polynomial is x7 + x6 + 1. Precise details of the scrambling operation are provided in the references. Note that the framing bytes and the identity bytes are not scrambled. All zeros may be continuously inserted (after scrambling) under register control for diagnostic purposes. 9.12 Transmit Line Overhead Processor The Transmit Line Overhead Processor (TLOP) provides line level alarm signal insertion, and line BIP-24/8 insertion (B2). APS Insert The APS Insert Block inserts the two automatic protection switch (APS) channel bytes in the Line Overhead (K1 and K2) into the transmit stream when enabled by an internal register. Line BIP Calculate The Line BIP Calculate Block calculates the line BIP-24/8 error detection code (B2) based on the line overhead and synchronous payload envelope of the transmit stream. The line BIP-24/8 code is a bit interleaved parity calculation using even parity. Details are provided in the references. The calculated BIP-24/8 code is inserted into the B2 byte positions of the following frame.
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BIP-24/8 errors may be continuously inserted under register control for diagnostic purposes. Line RDI Insert The Line RDI Insert Block controls the insertion of line remote defect indication. Line RDI insertion is enabled using the TLRDI input, or register control. Line RDI is inserted by transmitting the code 110 (binary) in bit positions 6, 7, and 8 of the K2 byte contained in the transmit stream. Line FEBE Insert The Line FEBE Insert Block accumulates line BIP-24/8 errors (B2) detected by the Receive Line Overhead Processor and encodes far end block error indications in the transmit Z2 byte. 9.13 Transport Overhead Insert Port The Transport Overhead Insert Port allows the complete transport overhead to be inserted using input TTOH, along with the transport overhead clock, TTOHCLK, and the transport overhead frame position, TTOHFP The transport . overhead clock, TTOHCLK, is nominally a 5.184 MHz (STS-3c/STM-1 mode) or a 1.728 MHz (STS-1 mode) clock. The transport overhead enable signal, TTOHEN, controls the insertion of transport overhead from TTOH. The state of the TTOHEN input determines whether the data sampled on TTOH, or the default overhead byte values (shown in Figure 7 and Figure 8) are inserted in the transmit stream. For example, when configured for STS-3c (STM-1) mode, a high level on TTOHEN during the section user channel (F1) bit positions causes the eight values shifted in the TTOH input to be inserted in the F1 byte position in the transmit stream. A low level on TTOHEN during the section user channel bit positions causes the default value (0x00) to be inserted in the transmit stream. During the H1, H2, B1 and B2 byte positions in the TTOH stream, a high level on TTOHEN enables an error insertion mask. While the error mask is enabled, a high level on TTOH causes the corresponding bit in the H1, H2, B1 or B2 byte to be inverted. A low level on TTOH causes the corresponding bit in the H1, H2, B1 or B2 byte to be transmitted uncorrupted.
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Figure 7
- STS-3c Default Transport Overhead Values
A1 A2 A2 A2 J0 Z0 Z0 A1 A1 (0xF6) (0xF6) (0xF6) (0x28) (0x28) (0x28) (0x01) (0x02) (0x03) B1 (*) E1 F1 (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00)
D1 D2 D3 (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) H1 H1 H1 H2 H2 H2 H3 H3 H3 (0x62) (0x93) (0x93) (0x0A) (0xFF) (0xFF) (0x00) (0x00) (0x00) B2 (*) B2 (*) B2 (*) K1 K2 (0x00) (0x00) (0x00) (0x00) (0x00) (0x00)
D4 D5 D6 (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) D7 D8 D9 (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) D10 D11 D12 (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) (0x00) S1 Z1 Z1 Z2 Z2 (0x00) (0x00) (0x00) (0x00) (0x00) M1 (*) E2 (0x00) (0x00) (0x00)
* : B1, B2 values depend on payload contents M1 value depends on incoming line bit errors
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Figure 8
- STS-1 Default Transport Overhead Values
A2 J0 A1 (0xF6) (0x28) (0x01) B1 (*) E1 F1 (0x00) (0x00)
D1 D2 D3 (0x00) (0x00) (0x00) H1 H2 H3 (0x62) (0x0A) (0x00) B2 (*) K1 K2 (0x00) (0x00)
D4 D5 D6 (0x00) (0x00) (0x00) D7 D8 D9 (0x00) (0x00) (0x00) D10 D11 D12 (0x00) (0x00) (0x00) S1 (0x00) M0 (*) E2 (0x00)
* : B1, B2 values depend on payload contents M0 value depends on incoming line bit errors 9.14 Transmit Path Overhead Processor The Transmit Path Overhead Processor (TPOP) provides transport frame alignment generation, pointer generation (H1, H2), path overhead insertion and the insertion of path level alarm signals. Pointer Generator The Pointer Generator Block generates the outgoing payload pointer (H1, H2) as specified in the references. The concatenation indication (the NDF field set to
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1001, I-bits and D-bits set to all ones, and unused bits set to all zeros) is inserted in the second and third pointer byte locations in the transmit stream. 1. A "normal pointer value" locates the start of the SPE. Note: 0 "normal pointer value" 782, and the new data flag (NDF) field is set to 0110. Note that values greater than 782 may be inserted, using internal registers, to generate a loss of pointer alarm in downstream circuitry. 2. Arbitrary "pointer values" may be generated using internal registers. These new values may optionally be accompanied by a programmable new data flag. New data flags may also be generated independently using internal registers. 3. Positive pointer movements may be generated using a bit in an internal register. A positive pointer movement is generated by inverting the five I-bits of the pointer word. The SPE is not inserted during the positive stuff opportunity byte position, and the pointer value is incremented by one. Positive pointer movements may be inserted once per frame for diagnostic purposes. 4. Negative pointer movements may be generated using a bit in an internal register. A negative pointer movement is generated by inverting the five Dbits of the pointer word. The SPE is inserted during the negative stuff opportunity byte position , the H3 byte, and the pointer value is decremented by one. Negative pointer movements may be inserted once per frame for diagnostic purposes. The pointer value is used to insert the path overhead into the transmit stream. The current pointer value may be read via internal registers. BIP-8 Calculate The BIP-8 Calculate Block performs a path bit interleaved parity calculation on the SPE of the transmit stream. Details are provided in the references. The resulting parity byte is inserted in the path BIP-8 (B3) byte position of the subsequent frame. BIP-8 errors may be continuously inserted under register control for diagnostic purposes. FEBE Calculate The FEBE Calculate Block accumulates far end block errors on a per frame basis, and inserts the accumulated value (up to maximum value of eight) in the
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FEBE bit positions of the path status (G1) byte. The FEBE information is derived from path BIP-8 errors detected by the receive path overhead processor, RPOP . Far end block errors may be inserted under register control for diagnostic purposes. 9.15 Path Overhead Insert The Path Overhead Insert Port allows the complete path overhead to be inserted using input TPOH, along with the path overhead clock, TPOHCLK, and the path overhead frame position, TPOHFP The path overhead clock, TPOHCLK, is . nominally a 576 kHz clock. The state of the TPOHEN input, together with an internal register, determines whether the data sampled on TPOH, or the default path overhead byte values (shown in Figure 9) are inserted in the transmit stream. For example, a high level on TPOHEN during the path signal label (C2) bit positions causes the eight values shifted in on TPOH to be inserted in the C2 byte position in the transmit stream. A low level on TPOHEN during the path signal label bit positions causes the default value (0x13) to be inserted in the transmit stream. During the B3 byte position in the TPOH stream, a high level on TPOHEN enables an error insertion mask. While the error mask is enabled, a high level on input TPOH causes the corresponding bit in the B3 byte to be inverted. A low level on TPOH causes the corresponding bit in the B3 byte to be transmitted uncorrupted.
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Figure 9
- Default Path Overhead Values
J1 (0x00) B3 (*) C2 (0x13) G1 (*) F2 (0x00) H4 (0x00) Z3 (0x00) Z4 (0x00) Z5 (0x00) * : B3 value depends on payload contents G1 value depends on incoming path bit errors 9.16 Transmit ATM Cell Processor The Transmit ATM Cell Processor (TACP) provides rate adaptation via idle/unassigned cell insertion, provides HCS generation and insertion, and performs ATM cell scrambling. The TACP contains a four cell transmit FIFO. An idle or unassigned cell is transmitted if a complete ATM cell has not been written into the FIFO.
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Idle/Unassigned Cell Generator The Idle/Unassigned Cell Generator inserts idle or unassigned cells into the cell stream when enabled. Registers are provided to program the GFC, PTI, and CLP fields of the idle cell header and the idle cell payload. The idle cell HCS is automatically calculated and inserted. Scrambler The Scrambler scrambles the 48 octet information field. Scrambling is performed using a parallel implementation of the self synchronous scrambler described in the references. The cell headers are transmitted unscrambled, and the scrambler may optionally be disabled. HCS Generator The HCS Generator performs a CRC-8 calculation over the first four header octets. A parallel implementation of the polynomial, x8+x2+x+1, is used. The coset polynomial, x6+x4+x2+1, is added (modulo 2) to the residue. The HCS Generator optionally inserts the result into the fifth octet of the header. GFC Insertion Port The GFC Insertion Port provides the ability to insert the GFC value downstream of the FIFO. The four GFC bits are received on a serial stream that is synchronized to the transmit cell by a framing pulse. The GFC enable register bits control the insertion of each serial bit. If the enable is cleared, the default GFC value is inserted. For idle/unassigned cells, the default is the contents of the TACP Idle/Unassigned Cell Header Control register. For assigned cells, the default is the value received from TDAT[15:0]. Transmit FIFO The Transmit FIFO provides FIFO management and the synchronous interface between the S/UNI-PLUS device and the external environment. The transmit FIFO can accommodate four cells. It provides for the separation of the STS-3c/1 (STM-1) line or physical layer timing from the ATM layer timing. The FIFO supports two data structures. The first data structure consists of twenty-seven 16-bit words comprising the five octet cell header, a cell header
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error control octet and the forty-eight octet payload. The second data structure consists of fifty-three 8-bit words comprising the five octet cell header and the forty-eight octet payload. Refer to the Operation section for more detail on these data structures. Management functions include filling the transmit FIFO, indicating when cells are available to be written to the transmit FIFO, maintaining the transmit FIFO read and write pointers, and detecting a FIFO overrun condition. The FIFO depth can be programmed to be one to four cells deep. The TCA output signal transitions low to indicate a full FIFO when the FIFO contains the same number of cells as the programmed FIFO depth. Note, a cell is not transmitted by the S/UNI-PLUS until the full cell has been written into the FIFO. When the FIFO is full as indicated by TCA and the upstream device writes into the FIFO, the TACP indicates a FIFO overrun condition using a maskable interrupt and register bits. The offending write and all subsequent writes are ignored until there is room in the FIFO. The FIFO interface provided to the system is a synchronous interface emulating commercial synchronous FIFOs. All transmit FIFO signals, TSOC, TWRENB, TCA, TXPRTY[1:0] and TDAT[15:0] are either sampled or updated on the rising edge of the TFCLK clock input. 9.17 SONET/SDH Section and Path Trace Buffers The SONET/SDH Section Trace Buffer (SSTB) block and the SONET/SDH Path Trace Buffer (SPTB) block are identical. The blocks can handle both 64-byte CLLI messages in SONET and 16-byte E.164 messages in SDH. The generic SONET/SDH Trace Buffer (STB) block is described below. 9.17.1 Receive Trace Buffer (RTB) The RTB consists of two parts: the Trace Message Receiver and the Overhead Byte Receiver. 1. Trace Message Receiver: The Trace Message Receiver (TMR) processes the trace message, and consists of three sub-processes: Framer, Persistency, and Compare. Framer:
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The TMR handles the incoming 16-byte message by synchronizing to the byte with the most significant bit set high, and places that byte in the first location in the capture page of the internal RAM. In the case of the 64-byte message, the TMR synchronizes to the trailing carriage return (0x0D), line feed (0x0A) sequence and places the next byte in the first location in the capture page of the internal RAM. The Framer block maintains an internal representation of the resulting 16-byte or 64-byte "frame" cycle. If the phase of the start of frame shifts, the framer adjusts accordingly and resets the persistency counter and increments the unstable counter. Frame synchronization may be disabled, in which case the RAM acts as a circular buffer. Persistency: The Persistency process checks for repeated reception of the same 16-byte or 64-byte trace message. An unstable counter is incremented for each message that differs from the previous received message. For example, a single corrupted message in a field of constant messages causes the unstable count to increment twice, once on receipt of the corrupted message, and again on the next (uncorrupted) message. A section/path trace message unstable alarm is declared when the count reaches eight. The persistency counter is reset to zero, the unstable alarm is removed, and the trace message is accepted when the same 16-byte or 64-byte message is received three or five times consecutively (as determined by an internal register bit). The accepted message is passed to the Compare process for comparison with the expected message. Compare: A receive trace message mismatch alarm is declared if the accepted message (i.e. the message that passed the persistency check) does not match the expected message (previously downloaded to the receive expected page by the microprocessor). The mismatch alarm is removed if the accepted message is all-zero, or if the accepted message is identical to the expected message. 2. Overhead Byte Receiver: The Overhead Byte Receiver (OBR) processes the path signal label byte (C2). The OBR consists of two sub-processes: Persistency and Compare.
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Persistency: The Persistency process checks for the repeated reception of the same C2 byte. An unstable counter is incremented for each received C2 byte that differs from the byte received in the previous frame. For example, a single corrupted byte value in a sequence of constant values causes the unstable count to increment twice, once on receipt of the corrupted value, and again on the next (uncorrupted) value. A path signal label unstable alarm or a synchronization status unstable alarm is declared when either unstable counter reaches five. The unstable counter is reset to zero, the unstable alarm is removed, and the byte value is accepted when the same label is received in five consecutive frames. The accepted value is passed to the Compare process for comparison with the expected value. Compare: A path signal label mismatch alarm or a synchronization status mismatch alarm is declared if the accepted C2 byte (i.e. the byte value that has passed the persistency check) does not match the expected C2 byte (previously downloaded by the microprocessor). The OBR mismatch mechanism follows the following table:
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Table 1 Expect 00 00 00 01 01 01 XX XX XX XX Note:
Receive 00 01 XX 00 01 XX 00 01 XX YY Action Match Mismatch Mismatch Mismatch Match Match Mismatch Match Match Mismatch
XX, YY = anything except 00H or 01H (XX not equal YY). 9.17.2 Transmit Trace Buffer (TTB) The TTB sources the 16-byte or 64-byte trace identifier message. The TTB contains one page of transmit trace identifier message memory. Identifier message data bytes are written by the microprocessor into the message buffer and inserted in the transmit stream. When the microprocessor is updating the transmit page buffer, the TTB may be programmed to transmit null characters to prevent transmission of partial messages. 9.18 Drop Side Interface
9.18.1 Receive Interface The drop side receive interface can be accessed through a generic 19-bit wide interface. External circuitry is notified, using the RCA signal, when a cell is available in the receive FIFO. External circuitry may then read the cell from the
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buffer as a word wide stream (along with a bit marking the first word of the cell) at instantaneous rates of up to 52 MHz. The cell data structure supported is described in the Operation section. 9.18.2 Transmit Interface The drop side transmit interface can be accessed through a generic 19-bit wide interface. External circuitry is notified using the TCA signal when a cell may be written to the transmit FIFO. The cell is written to the FIFO as a word wide stream (along with a bit marking the first word of the cell) at instantaneous rates of up to 52 MHz. The cell data structure supported is described in the Operation section. 9.19 Parallel I/O Port The Parallel Input/Output Port block provides four generic outputs and four generic inputs that can be used to control and monitor front end PMD devices. 9.20 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI-PLUS identification code is 053470CD hexadecimal. 9.21 Microprocessor Interface The microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the S/UNI-PLUS.
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9.22
Register Memory Map Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16-0x17 0x18 0x19 Register S/UNI-PLUS Master Reset and Identity / Load Performance Meters S/UNI-PLUS Master Configuration S/UNI-PLUS Master Interrupt Status S/UNI-PLUS Master Control S/UNI-PLUS Master Auto Alarm/Monitor S/UNI-PLUS Clock Synthesis Control and Status S/UNI-PLUS Clock Recovery Control and Status S/UNI-PLUS Parallel I/O Port S/UNI-PLUS Parallel Input Port Interrupt S/UNI-PLUS Parallel Input Port Enable S/UNI-PLUS Transmit J0/Z0 S/UNI-PLUS APS Control/Status S/UNI-PLUS Receive K1 S/UNI-PLUS Receive K2 S/UNI-PLUS Receive S1 S/UNI-PLUS Transmit S1 RSOP Control/Interrupt Enable RSOP Status/Interrupt Status RSOP Section BIP-8 LSB RSOP Section BIP-8 MSB TSOP Control TSOP Diagnostic TSOP Reserved RLOP Control/Status RLOP Interrupt Enable/Interrupt Status
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Address 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24-0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E-0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38
Register RLOP Line BIP-24/8 LSB RLOP Line BIP-24/8 RLOP Line BIP-24/8 MSB RLOP Line FEBE LSB RLOP Line FEBE RLOP Line FEBE MSB TLOP Control TLOP Diagnostic TLOP Transmit K1 TLOP Transmit K2 Reserved SSTB Control SSTB Status SSTB Indirect Address SSTB Indirect Data SSTB Reserved SSTB Reserved SSTB Reserved RPOP Status/Control RPOP Interrupt Status RPOP Pointer Interrupt Status RPOP Interrupt Enable RPOP Pointer Interrupt Enable RPOP Pointer LSB RPOP Pointer MSB and RDI Filter Control RPOP Path Signal Label RPOP Path BIP-8 LSB
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Address 0x39 0x3A 0x3B 0x3C 0x3D 0x3E-0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E-0x4F 0x50 0x51 0x52 0x53 0x54 0x55
Register RPOP Path BIP-8 MSB RPOP Path FEBE LSB RPOP Path FEBE MSB RPOP Auxiliary RDI RPOP Error Event Control RPOP Reserved TPOP Control/Diagnostic TPOP Pointer Control TPOP Reserved TPOP Current Pointer LSB TPOP Current Pointer MSB TPOP Arbitrary Pointer LSB TPOP Arbitrary Pointer MSB TPOP Path Trace TPOP Path Signal Label TPOP Path Status TPOP Path User Channel TPOP Path Growth #1 (Z3) TPOP Path Growth #2 (Z4) TPOP Path Growth #3 (Z5) TPOP Reserved RACP Control RACP Interrupt Status RACP Interrupt Enable/Control RACP Match Header Pattern RACP Match Header Mask RACP Correctable HCS Error Count (LSB)
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Address 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D-0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E-0x6F 0x70 0x71 0x72 0x73
Register RACP Correctable HCS Error Count (MSB) RACP Uncorrectable HCS Error Count (LSB) RACP Uncorrectable HCS Error Count (MSB) RACP Receive Cell Counter (LSB) RACP Receive Cell Counter RACP Receive Cell Counter (MSB) RACP GFC Control RACP Reserved TACP Control/Status TACP Idle/Unassigned Cell Header Pattern TACP Idle/Unassigned Cell Payload Octet Pattern TACP FIFO Control TACP Transmit Cell Counter (LSB) TACP Transmit Cell Counter TACP Transmit Cell Counter (MSB) TACP Fixed Stuff / GFC SPTB Control SPTB Status SPTB Indirect Address SPTB Indirect Data SPTB Expected Path Signal Label SPTB Path Signal Label Status SPTB Reserved BERM Control BERM Interrupt BERM Line BIP Accumulation Period LSB BERM Line BIP Accumulation Period MSB
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Address 0x74 0x75 0x76-0x7F 0x80 0x81-0xFF
Register BERM Line BIP Threshold LSB BERM Line BIP Threshold MSB Reserved S/UNI Master Test Reserved for Test
For all register accesses, CSB must be low.
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10
NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the S/UNI-PLUS. Normal mode registers (as opposed to test mode registers) are selected when TRS (A[7]) is low. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the S/UNI-PLUS to determine the programming state of the block. 3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect S/UNI-PLUS operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-PLUS operates as intended, reserved register bits must only be written with logic zero. Similarly, writing to reserved registers should be avoided.
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Register 0x00: S/UNI-PLUS Master Reset and Identity / Load Performance Meters Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R R R R R R R Function RESET TYPE[2] TYPE[1] TYPE[0] TIP ID[2] ID[1] ID[0] Default 0 1 0 0 X 0 0 0
This register allows the revision of the S/UNI-PLUS to be read by software permitting graceful migration to newer, feature enhanced versions of the S/UNI-PLUS. ID[2:0]: The ID bits can be read to provide a binary S/UNI-PLUS revision number. TIP: The TIP bit is set to a logic one when any value is written to this register. Such a write initiates an accumulation interval transfer and loads all the performance meter registers in the RSOP RLOP RPOP RACP and TACP , , , , blocks. TIP remains high while the transfer is in progress, and is set to a logic zero when the transfer is complete. TIP can be polled by a microprocessor to determine when the accumulation interval transfer is complete. TYPE[2:0]: The TYPE bits can be read to distinguish the S/UNI-PLUS from the other members of the S/UNI family of devices. RESET: The RESET bit allows the S/UNI-PLUS to be reset under software control. If the RESET bit is a logic one, the entire S/UNI-PLUS is held in reset. This bit is not self-clearing; therefore, a logic zero must be written to bring the
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S/UNI-PLUS out of reset. Holding the S/UNI-PLUS in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. Otherwise the effect of a software reset is equivalent to that of a hardware reset.
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Register 0x01: S/UNI-PLUS Master Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RRATE[1:0]: The RRATE[1:0] bits select the operation rate of the S/UNI-PLUS's receive side. The default configuration selects STS-3c rate operation. The S/UNI-PLUS will not operate correctly if a Reserved mode is selected. RRATE[1:0] 00 01 10 11 TRATE[1:0]: The TRATE[1:0] bits select the operation rate of the S/UNI-PLUS's transmit side. The default configuration selects STS-3c rate operation. The S/UNI-PLUS will not operate correctly if a Reserved mode is selected. TRATE[1:0] 00 01 MODE Reserved Reserved MODE Reserved Reserved 51.84 Mbit/s, STS-1 155.52 Mbit/s, STS-3c/STM-1 Type R/W R/W R/W R/W R/W R/W R/W R/W Function TPTBEN TSTBEN SDH_J0/Z0 FIXPTR TRATE[1] TRATE[0] RRATE[1] RRATE[0] Default 0 0 0 1 1 1 1 1
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TRATE[1:0] 10 11 FIXPTR:
MODE 51.84 Mbit/s, STS-1 155.52 Mbit/s, STS-3c/STM-1
The FIXPTR bit disables transmit payload pointer adjustments. If the FIXPTR bit is a logic one, the transmit payload pointer is set at 522. If FIXPTR is a logic zero, the payload pointer is controlled by the contents of the TPOP Pointer Control register. SDH_J0/Z0 The SDH_J0/Z0 bit selects whether to insert SONET or SDH formatted section overhead bytes into the transmit stream. When SDH_J0/Z0 is a logic one, SDH format section overhead bytes are selected for insertion. For this case, the J0 byte (in STS-1) or the J0/Z0 bytes (in STS-3c) in the transmitted signal are forced to the value programmed in the S/UNI-PLUS Transmit J0/Z0 register. When SDH_J0/Z0 is a logic zero, SONET formatted section overhead bytes are selected for insertion. For this case, the J0/Z0 bytes of the transmitted STS-N signal are numbered incrementally from 1 to N (i.e., the J0 byte will be set to 0x01, the first Z0 will be set to 0x02, the second Z0 will be set to 0x03, etc.). Note, for both cases, the transmit section trace buffer enable bit, TSTBEN can be used to overwrite the J0 byte of the transmitted STS-3c/1 (STM-1) signal. TSTBEN The TSTBEN bit controls whether the section trace message stored in the SSTB block is inserted into the transmit stream (i.e. the J0 byte). When TSTBEN is a logic one, the message stored in the SSTB is inserted into the transmit stream. When TSTBEN is a logic zero, the section trace message is supplied by the TSOP block or via the TTOH input. TPTBEN The TPTBEN bit controls whether the path trace message stored in the SPTB block is inserted into the transmit stream (i.e. the J1 byte). When TPTBEN is a logic one, the message stored in the SPTB is inserted into the transmit stream. When TPTBEN is a logic zero, the path trace message is supplied by the TPOP block or via the TPOH input.
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Register 0x02: S/UNI-PLUS Master Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function MISCI SSTBI SPTBI TACPI RACPI RPOPI RLOPI RSOPI Default X X X X X X X X
This register allows the source of an active interrupt to be identified down to the block level. Further register accesses are required for the block in question to determine the cause of an active interrupt and to acknowledge the interrupt source. RSOPI: The RSOPI bit is a logic one when an interrupt request is active from the RSOP block. The RSOP interrupt sources are enabled in the RSOP Control/Interrupt Enable Register. RLOPI: The RLOPI bit is a logic one when an interrupt request is active from the RLOP block. The RLOP interrupt sources are enabled in the RLOP Interrupt Enable/Status Register. RPOPI: The RPOPI bit is a logic one when an interrupt request is active from the RPOP block. The RPOP interrupt sources are enabled in the RPOP Interrupt Enable Register. RACPI: The RACPI bit is a logic one when an interrupt request is active from the RACP block. The RACP interrupt sources are enabled in the RACP Interrupt Enable/Status Register.
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TACPI: The TACPI bit is a logic one when an interrupt request is active from the TACP block. The TACP interrupt sources are enabled in the TACP Interrupt Control/Status Register. SPTBI: The SPTBI bit is a logic one when an interrupt request is active from the SPTB block. The SPTB interrupt sources are enabled in the SPTB Control Register and the SPTB Path Signal Label Status Register. SSTBI: The SSTBI bit is a logic one when an interrupt request is active from the SSTB block. The SSTB interrupt sources are enabled in the SSTB Control Register and the SSTB Synchronization Message Status Register. MISCI: The MISCI bit is a logic one when an interrupt request is active from the Parallel Input/Output block, the S1 Change Block, the Clock Synthesis Block, the Clock Recovery Block, the BERM block or the APS Block. The Parallel Input/Output interrupt sources are enabled in the S/UNI-PLUS Parallel Input Port Enable Register. The S1 Change interrupt and the APS interrupt sources are enabled in the S/UNI-PLUS APS Control/Status Register. The Clock Synthesis interrupt soure is enabled in the S/UNI-PLUS Clock Synthesis Control and Status Register. The Clock Recovery interrupt soure is enabled in the S/UNI-PLUS Clock Recovery Control and Status Register. The BERM interrupt source is enabled in the BERM Control Register.
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Register 0x03: S/UNI-PLUS Master Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function TCAINV RCAINV RXDINV LLE SDLE PDLE TTIME[1] TTIME[0] Default 0 0 0 0 0 0 0 0
This register provides polarity control for outputs RCA and TCA, loopback control and transmit timing control. TTIME[1:0]: The TTIME[1:0] bits select the timing source for the transmit section of the S/UNI-PLUS. TTIME[1:0] 00 01 10 11 TIMING SOURCE TRCLK+ and TRCLKRRCLK+ and RRCLKLoop Timing Loop Timing
When Loop Timing is enabled, the transmitter timing is derived from the receiver inputs RXD+ and RXD- when clock recovery is enabled and from RRCLK+ and RRCLK- when clock recovery is disabled. PDLE: The PDLE bit enables the parallel diagnostic loopback. When PDLE is a logic one, the transmit parallel stream is connected to the receive stream. The loopback point is between the TPOP and the RPOP blocks. Blocks upstream
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of the loopback point continue to operate normally. For example line AIS may be inserted in the transmit stream upstream of the loopback point using the TSOP Control register. SDLE: The SDLE bit enables the serial diagnostic loopback. When SDLE is a logic one, the transmit serial stream is connected to the receive stream. The SDLE and the LLE bits should not be set high simultaneously. LLE: The LLE bit enables the S/UNI-PLUS line loopback. When LLE is a logic one, RXD+ and RXD- are connected internally to TXD+ and TXD- respectively. The SDLE and the LLE bits should not be set high simultaneously. RXDINV: The RXDINV bits select the polarity of the RXD+/- signals. The default configuration selects RXD+ (RXD-) to be high (low) when the receive stream contains a logic one. When RXDINV is a logic one, RXD+/- is inverted; RXD+(RXD-) is low (high) when the receive stream contains a logic one. RCAINV: The RCAINV bits select the active polarity of the RCA signal. The default configuration selects RCA to be active high, indicating that a received cell is available when high. When RCAINV is a logic one, the RCA signal becomes active low. TCAINV: The TCAINV bits select the active polarity of the TCA signal. The default configuration selects TCA to be active high, indicating that a cell is available in the transmit FIFO when high. When TCAINV is a logic one, the TCA signal becomes active low.
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Register 0x04: S/UNI-PLUS Master Auto Alarm/Monitor Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 AUTOPRDI The AUTOPRDI bit determines whether the path remote defect indication is sent immediately upon detection of an incoming alarm. When AUTOPRDI is a logic one, the path remote defect indication is inserted immediately upon declaration of loss of signal (LOS), loss of frame (LOF), line AIS (LAIS), loss of pointer (LOP), or STS path AIS (PAIS). AUTOLRDI The AUTOLRDI bit determines whether line remote defect indication (LRDI) is sent immediately upon detection of an incoming alarm. When AUTOLRDI is a logic one, line RDI is inserted immediately upon declaration of loss of signal (LOS), loss of frame (LOF), or line AIS (LAIS). AUTOFEBE The AUTOFEBE bit determines whether line and path far end block errors are sent upon detection of an incoming line and path BIP error events. When AUTOFEBE is a logic one, one line or path FEBE is inserted for each line or path BIP error event. When AUTOFEBE is a logic zero, incoming line or path BIP error events do not generate FEBE events. R R R R R/W R/W R/W Type Function Unused RFCLKA TFCLKA RRCLKA TRCLKA AUTOFEBE AUTOLRDI AUTOPRDI Default X X X X X 1 1 1
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TRCLKA: The TRCLK active bit monitors for low to high transitions on the TRCLK+ and TRCLK- inputs. TRCLKA is set high on a rising edge of TRCLK+/-, and is set low when this register is read. TTCLKA: The TTCLK active bit monitors for low to high transitions on the TTCLK+ and TTCLK- inputs. TTCLKA is set high on a rising edge of TTCLK+/-, and is set low when this register is read. TFCLKA: The TFCLK active bit monitors for low to high transitions on the TFCLK input. TFCLKA is set high on a rising edge of TFCLK, and is set low when this register is read. RFCLKA: The RFCLK active bit monitors for low to high transitions on the RFCLK input. RFCLKA is set high on a rising edge of RFCLK, and is set low when this register is read.
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Register 0x05: S/UNI-PLUS Clock Synthesis Control and Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R/W R/W Type Function Unused Unused Unused Unused TROOLV TROOLI TROOLE TREFSEL Default X X X X X X 0 0
This register controls the clock synthesis and reports the state of the transmit phase locked loop. TREFSEL: The transmit reference select (TREFSEL) bit determines the expected frequency of TRCLK+/- to synthesize the line clock frequency. If TREFSEL is a logic zero, the reference frequency must be 19.44 MHz. If TREFSEL is a logic one, the reference frequency must be 6.48 MHz. TREFSEL only has effect if the TBYP input is low. TROOLE: The TROOLE bit is an interrupt enable for the transmit reference out of lock status. When TROOLE is a logic one, an interrupt is generated when the TROOLV bit changes state. TROOLI: The TROOLI bit is the transmit reference out of lock interrupt status bit. TROOLI is a logic one when the TROOLV bit changes state. TROOLI is cleared when this register is read. TROOLV: The transmit reference out of lock status indicates the clock synthesis phase locked loop is unable to lock to the reference. TROOLV is a logic one if the
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divided down synthesized clock frequency not within 488 ppm of the transmit reference frequency.
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Register 0x06: S/UNI-PLUS Clock Recovery Control and Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R/W R/W Type Function Unused Unused Unused RROOLV RDOOLV RDOOLI RDOOLE RREFSEL Default X X X X X X 0 0
This register controls the clock recovery and reports the state of the receive phase locked loop. RREFSEL: The receive reference select (RREFSEL) bit determines the expected frequency of RRCLK+/-. If RREFSEL is a logic zero, the reference frequency is 19.44 MHz. If RREFSEL is a logic one, the reference frequency must be 6.48 MHz. RREFSEL only has effect if the RBYP input is low. RDOOLE: The RDOOLE bit is an interrupt enable for the receive data out of lock status. When RDOOLE is a logic one, an interrupt is generated when the RDOOLV bit changes state. RDOOLI: The RDOOLI bit is the receive data out of lock interrupt status bit. RDOOLI is a logic one when the RDOOLV bit changes state. RDOOLI is cleared when this register is read. RDOOLV: The receive data out of lock status indicates the clock recovery phase locked loop is unable to lock to the receive stream. RDOOLV is a logic one if the divided down recovered clock frequency not within 488 ppm of the RRCLK+/-
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frequency or if no transitions have occurred on the RXD+/- inputs for more than 80 bit periods. RROOLV: The receive reference out of lock status indicates the clock recovery phase locked loop is unable to lock to the receive reference (RRCLK+/-). RROOLV should be polled after a power up reset to determine when the CRU PLL is operational. When RROOLV is a logic 1, the CRU is unable to lock to the receive reference. When RROOLV is a logic 0, the CRU is locked to the receive reference. The RROOLV bit may remain set at logic 1 for several hundred milliseconds after the removal of the power on reset as the CRU PLL locks to the receive reference clock.
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Register 0x07: S/UNI-PLUS Parallel I/O Port Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIPV[3:0]: The PIPV[3:0] bits are real-time input port state indications. A logic one in any bit location indicates that the signal on the corresponding PIP[3:0] input is a logic one. A logic zero in any bit location indicates that the signal on the corresponding PIP[3:0] input is a logic zero. POP[3:0]: The values written to the POP[3:0] bit in the S/UNI-PLUS Parallel Output Port register directly correspond to the states set on the POP[3:0] output pins. This provides a generic port useful for controlling an external PMD device. The default states for this port are chosen so that POP[3:2] controls active high signals while POP[1:0] controls active low signals. Type R/W R/W R/W R/W R R R R Function POP[3] POP[2] POP[1] POP[0] PIPV[3] PIPV[2] PIPV[1] PIPV[0] Default 1 1 0 0 X X X X
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Register 0x08: S/UNI-PLUS Parallel Input Port Interrupt Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIPI[7:0]: The PIPI[7:0] bits are interrupt indications. A logic one in any bit location indicates that an event has occurred on the corresponding PIP[3:0] input. More specifically, a logic one in any of the PIPI[7:4] bit locations indicates that the signal on the corresponding PIP[3:0] input has transitioned from logic zero to logic one (i.e. upon detection of a rising edge); a logic one in any of the PIPI[3:0] bit locations indicates that the signal on the corresponding PIP[3:0] input has transitioned either from logic zero to logic one or from logic one to logic zero (i.e. upon a change of state). The PIPI[7:0] bits are cleared by reading this register. These register bits function independently from the S/UNI-PLUS Parallel Input Port Enable register bits. The PIPI[7:0] bits will indicate events occurring on the PIP[3:0] inputs regardless of whether or not these events are enabled to generate an interrupt. It is intended that the PIP[3:0] inputs monitor the status of an external PMD device. Type R R R R R R R R Function PIPI[7] PIPI[6] PIPI[5] PIPI[4] PIPI[3] PIPI[2] PIPI[1] PIPI[0] Default X X X X X X X X
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Register 0x09: S/UNI-PLUS Parallel Input Port Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIPE[7:0]: The PIPE[7:0] bits are interrupt enables. When a logic one is written to these locations, the occurrence of an event on the corresponding PIP[7:0] input activates the interrupt, INTB. The interrupt is cleared by reading the S/UNIPLUS Parallel Input Port Interrupt Register. When a logic zero is written to these locations, the occurrence of an event on the corresponding PIP[7:0] input is inhibited from activating the interrupt. Type R/W R/W R/W R/W R/W R/W R/W R/W Function PIPE[7] PIPE[6] PIPE[5] PIPE[4] PIPE[3] PIPE[2] PIPE[1] PIPE[0] Default 0 0 0 0 0 0 0 0
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Register 0x0A: S/UNI-PLUS Transmit J0/Z0 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 J0/Z0[7:0]: The value written to these bit positions is inserted into the J0/Z0 byte positions of the transmit stream when enabled using the SDH_J0/Z0 bit in the S/UNI-PLUS Master Configuration register. J0/Z0[7] is the most significant bit, corresponding to the first bit (bit 1) transmitted. J0/Z0[0] is the least significant bit, corresponding to the last bit (bit 8) transmitted. Type R/W R/W R/W R/W R/W R/W R/W R/W Function J0/Z0[7] J0/Z0[6] J0/Z0[5] J0/Z0[4] J0/Z0[3] J0/Z0[2] J0/Z0[1] J0/Z0[0] Default 1 1 0 0 1 1 0 0
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Register 0x0B: S/UNI-PLUS APS Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PSBFV: The PSBFV bit indicates the protection switching byte failure alarm state. The alarm is declared (PSBFV is a logic one) when twelve successive frames have been received where no three consecutive frames contain identical K1 bytes. The alarm is removed (PSBFV is a logic zero) when three consecutive frames containing identical K1 bytes have been received. COAPSI: The COAPSI bit is a logic one when a new APS code value has been extracted into the S/UNI-PLUS Receive K1/K2 Registers. The registers are updated when the same new K1/K2 byte values are observed for three consecutive frames. This bit is cleared when the S/UNI-PLUS APS Control/Status Register is read. PSBFI: The PSBFI bit is a logic one when the protection switching byte failure alarm is declared or removed. This bit is cleared when the S/UNI-PLUS APS Control/Status Register is read. S1I: The S1I bit is a logic one when a new S1 byte value has been extracted into the S/UNI-PLUS Receive S1 Register. The register is updated when a S1 byte value is extracted that is different than the S1 byte value extracted in the R Type R/W R/W R/W R R R Function PSBFE COAPSE S1E S1I PSBFI COAPSI Unused PSBFV Default 0 0 0 X X X X X
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previous frame. This bit is cleared when the S/UNI-PLUS APS Control/Status Register is read. S1E: The change of S1 interrupt enable is an interrupt mask for changes in the receive S1 byte value. When S1E is a logic one, an interrupt is generated when the extracted S1 byte is different from the S1 byte extracted in the previous frame. COAPSE: The change of APS byte interrupt enable is an interrupt mask for events detected by the receive APS processor. When COAPSE is a logic one, an interrupt is generated when a new K1/K2 code value has been extracted into the S/UNI-PLUS Receive K1/K2 Registers. PSBFE: The change of protection switch byte failure alarm interrupt enable is an interrupt mask for events detected by the receive APS processor. When PSBFE is a logic one, an interrupt is generated upon a change in the protection switch byte failure alarm state.
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Register 0x0C: S/UNI-PLUS Receive K1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K1[7:0]: The K1[7:0] bits contain the current K1 code value. The contents of this register are updated when a new K1 code value (different from the current K1 code value) has been received for three consecutive frames. An interrupt may be generated when a new code value is received (using the COAPSE bit in the S/UNI-PLUS APS Control Register). K1[7] is the most significant bit, corresponding to the first bit (bit 1) received. K1[0] is the least significant bit, corresponding to the last bit (bit 8) received. Type R R R R R R R R Function K1[7] K1[6] K1[5] K1[4] K1[3] K1[2] K1[1] K1[0] Default X X X X X X X X
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Register 0x0D: S/UNI-PLUS Receive K2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K2[7:0]: The K2[7:0] bits contain the current K2 code value. The contents of this register are updated when a new K2 code value (different from the current K2 code value) has been received for three consecutive frames. An interrupt may be generated when a new code value is received (using the COAPSE bit in the S/UNI-PLUS APS Control Register). K2[7] is the most significant bit, corresponding to the first bit (bit 1) received. K2[0] is the least significant bit, corresponding to the last bit (bit 8) received. Type R R R R R R R R Function K2[7] K2[6] K2[5] K2[4] K2[3] K2[2] K2[1] K2[0] Default X X X X X X X X
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Register 0x0E: S/UNI-PLUS Receive S1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S1[7:0]: The first S1 byte contained in the receive stream is extracted into this register. The S1 byte is used to carry synchronization status messages between line terminating network elements. S1[7] is the most significant bit, corresponding to the first bit (bit 1) received. S1[0] is the least significant bit, corresponding to the last bit (bit 8) received. An interrupt may be generated when a byte value is received that differs from the value extracted in the previous frame using the S1E bit in the APS Control/Status Register. Type R R R R R R R R Function S1[7] S1[6] S1[5] S1[4] S1[3] S1[2] S1[1] S1[0] Default X X X X X X X X
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Register 0x0F: S/UNI-PLUS Transmit S1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S1[7:0]: The value written to these bit positions is inserted in the first S1 byte position of the transmit stream. The S1 byte is used to carry synchronization status messages between line terminating network elements. S1[7] is the most significant bit, corresponding to the first bit (bit 1) transmitted. S1[0] is the least significant bit, corresponding to the last bit (bit 8) transmitted. Type R/W R/W R/W R/W R/W R/W R/W R/W Function S1[7] S1[6] S1[5] S1[4] S1[3] S1[2] S1[1] S1[0] Default 0 0 0 0 0 0 0 0
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Register 0x10: RSOP Control/Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFE: The OOFE bit is an interrupt enable for the out of frame alarm. When OOFE is set to logic one, an interrupt is generated when the out of frame alarm changes state. LOFE: The LOFE bit is an interrupt enable for the loss of frame alarm. When LOFE is a logic one, an interrupt is generated when the loss of frame alarm changes state. LOSE: The LOSE bit is an interrupt enable for the loss of signal alarm. When LOSE is a logic one, an interrupt is generated when the loss of signal alarm changes state. BIPEE: The BIPEE bit is an interrupt enable for the section BIP-8 errors. When BIPEE is a logic one, an interrupt is generated when a section BIP-8 error (B1) is detected. FPSEL: The FPSEL bit selects the framing pattern used for in-frame validation, and out-of-frame declaration. When FPSEL is a logic one, the framing pattern Type R/W R/W W R/W R/W R/W R/W R/W Function BIPWORD DDS FOOF FPSEL BIPEE LOSE LOFE OOFE Default 0 0 X 0 0 0 0 0
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consists of the first A1 byte, and the first four bits of the first A2 byte (12 bits total). In the presence of a 10-3 bit error rate, the mean time between OOF declarations is 103 minutes for both STS-1 and STS-3c/STM-1 rates. When FPSEL is a logic zero, the framing pattern consists of all the A1 bytes and all the A2 bytes (48 bits for STS-3c/STM-1 and 16 bits for STS-1). In the presence of a 10-3 bit error rate, the mean time between OOF declarations is 26 seconds for STS-3c/STM-1, and 33 minutes for STS-1. FOOF: The FOOF bit controls the framing of the RSOP When a logic one is written . to FOOF, the RSOP is forced out of frame at the next frame boundary. The FOOF bit is a write only bit, register reads may yield a logic one or a logic zero. DDS: The DDS bit enables the frame synchronous descrambling of the receive stream. When DDS is a logic one, descrambling is disabled. When DDS is a logic zero, descrambling is enabled. BIPWORD: The BIPWORD bit controls the accumulation of B1 block errors. When BIPWORD is a logic one, one or more B1 errors per frame result in a single error accumulated in the B1 error counter. When BIPWORD is a logic zero, each B1 error is accumulated in the B1 error counter.
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Register 0x11: RSOP Status/Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFV: The OOFV bit is read to determine the out of frame state. When OOFV is a logic one, the S/UNI-PLUS is out-of-frame. When OOFV is a logic zero, the S/UNI-PLUS is in-frame. LOFV: The LOFV bit is read to determine the loss of frame state. When LOFV is a logic one, the S/UNI-PLUS has declared loss of frame. LOSV: The LOSV bit is read to determine the loss of signal state. When LOSV is a logic one, the S/UNI-PLUS has declared loss of signal. OOFI: The OOFI bit is the out-of-frame interrupt status bit. OOFI is a logic one when a change in the out-of-frame state occurs. This bit is cleared when this register is read. LOFI: The LOFI bit is the loss of frame interrupt status bit. LOFI is a logic one when a change in the loss of frame state occurs. This bit is cleared when this register is read. R R R R R R R Type Function Unused BIPEI LOSI LOFI OOFI LOSV LOFV OOFV Default X X X X X X X X
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LOSI: The LOSI bit is the loss of signal interrupt status bit. LOSI is a logic one when a change in the loss of signal state occurs. This bit is cleared when this register is read. BIPEI: The BIPEI bit is the section BIP-8 interrupt status bit. BIPEI is a logic one when a B1 error is detected. This bit is cleared when this register is read.
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Register 0x12: RSOP Section BIP-8 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function SBE[7] SBE[6] SBE[5] SBE[4] SBE[3] SBE[2] SBE[1] SBE[0] Default X X X X X X X X
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Register 0x13: RSOP Section BIP-8 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SBE[15:0]: SBE[15:0] represent the number of B1 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RSOP Section BIP-8 Register addresses. Such a write transfers the internally accumulated error count to the Section BIP-8 registers within approximately 2 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. Type R R R R R R R R Function SBE[15] SBE[14] SBE[13] SBE[12] SBE[11] SBE[10] SBE[9] SBE[8] Default X X X X X X X X
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Register 0x14: TSOP Control Bit Bit 7 Bit 6 Bit 5 Bit 3 Bit 3 Bit 2 Bit 1 Bit 0 LAIS: The LAIS bit controls the insertion of line alarm indication signal (LAIS). When LAIS is a logic one, the TSOP inserts AIS into the transmit stream. Activation or deactivation of line AIS insertion is synchronized to frame boundaries. Line AIS insertion results in all bytes of the SONET frame being set to 0xFF prior to scrambling except for the section overhead. The LAIS bit is logically ORed with the external TLAIS input. DS: The DS bit enables the frame synchronous scrambling of the transmit stream. When DS is a logic one, scrambling is disabled. When DS is a logic zero, scrambling is enabled. Reserved: The reserved bits must be programmed to logic zero for proper operation. R/W R/W R/W R/W R/W R/W R/W Type Function Unused DS Reserved Reserved Reserved Reserved Reserved LAIS Default X 0 0 0 0 0 0 0
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Register 0x15: TSOP Diagnostic Bit Bit 7 Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DFP: The DFP bit controls the insertion of a single bit error continuously in the most significant bit (bit 1) of the A1 section overhead framing byte. When DFP is a logic one, the A1 bytes are set to 0x76 instead of 0xF6. DBIP8: The DBIP8 bit controls the insertion of bit errors continuously in the B1 byte. When DBIP8 is a logic one, the B1 byte is inverted. DLOS: The DLOS bit controls the insertion of all zeros in the transmit stream. When DLOS is a logic one, the transmit stream is forced to 0x00. R/W R/W R/W Type Function Unused Unused Unused Unused Unused DLOS DBIP8 DFP Default X X X X X 0 0 0
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Register 0x18: RLOP Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDIV: The LRDIV bit is read to determine the remote defect indication state. When LRDIV is a logic one, the S/UNI-PLUS has declared line RDI. LAISV: The LAISV bit is read to determine the line AIS state. When LAISV is a logic one, the S/UNI-PLUS has declared line AIS. FEBEGEN: The FEBEGEN bit controls the indication of B2 errors reported to the TLOP block for insertion as FEBEs. When FEBEGEN is a logic one, a single FEBE is indicated each frame whenever one or more B2 errors occur during that frame. When FEBEGEN is a logic zero, a single FEBE is indicated for each B2 bit error that occurs during that frame (maximum of 24 FEBEs per frame for STS-3c/STM-1). The accumulation of B2 error events functions independently and is controlled by the BIPWORD register bit. LRDIDET: The LRDIDET bit determines the line RDI alarm detection algorithm. When LRDIDET is a logic one, line RDI is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for three consecutive frames. When LRDIDET is a logic zero, line RDI is declared when a 110 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for five consecutive frames. R R Type R/W R/W R/W R/W R/W Function BIPWORD ALLONES AISDET LRDIDET FEBEGEN Unused LAISV LRDIV Default 0 0 0 0 0 X X X
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AISDET: The AISDET bit determines the line AIS alarm detection algorithm. When AISDET is a logic one, line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for three consecutive frames. When AISDET is a logic zero, line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2 byte for five consecutive frames. ALLONES: The ALLONES bit controls the conditioning that occurs whenever line AIS is detected in the recovered data. When ALLONES is a logic one, the recovered data is forced to logic one immediately when the line AIS alarm is detected. When line AIS is removed, the recovered data is passed unconditioned. When ALLONES is a logic zero, recovered data conditioning is disabled regardless of the state of the line AIS alarm. BIPWORD: The BIPWORD bit controls the accumulation of B2 block errors. When BIPWORD is a logic one, one or more B2 errors per frame result in a single error accumulated in the B2 error counter. When BIPWORD is a logic zero, each B2 error is accumulated in the B2 error counter.
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Register 0x19: RLOP Interrupt Enable/Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDII: The LRDII bit is the line remote defect indication interrupt status bit. LRDII is a logic one when a change in the line RDI state occurs. This bit is cleared when this register is read. LAISI: The LAISI bit is the line AIS interrupt status bit. LAISI is a logic one when a change in the line AIS state occurs. This bit is cleared when this register is read. BIPEI: The BIPEI bit is the line BIP-24/8 interrupt status bit. BIPEI is a logic one when a B2 error is detected. This bit is cleared when this register is read. FEBEI: The FEBEI bit is the line far end block error interrupt status bit. FEBEI is a logic one when a line layer FEBE (M0/M1) is detected. This bit is cleared when this register is read. LRDIE: The LRDIE bit is an interrupt enable for the line remote defect indication alarm. When LRDIE is a logic one, an interrupt is generated when the line RDI state changes. Type R/W R/W R/W R/W R R R R Function FEBEE BIPEE LAISE LRDIE FEBEI BIPEI LAISI LRDII Default 0 0 0 0 X X X X
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LAISE: The LAISE bit is an interrupt enable for line AIS. When LAISE is a logic one, an interrupt is generated when line AIS changes state. BIPEE: The BIPEE bit is an interrupt enable for the line BIP-24/8 errors. When BIPEE is a logic one, an interrupt is generated when a B2 error is detected. FEBEE: The FEBEE bit is an interrupt enable for the line far end block errors. When FEBEE is a logic one, an interrupt is generated when a FEBE is detected.
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Register 0x1A: RLOP Line BIP-24/8 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LBE[7] LBE[6] LBE[5] LBE[4] LBE[3] LBE[2] LBE[1] LBE[0] Default X X X X X X X X
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Register 0x1B: RLOP Line BIP-24/8 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LBE[15] LBE[14] LBE[13] LBE[12] LBE[11] LBE[10] LBE[9] LBE[8] Default X X X X X X X X
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Register 0x1C: RLOP Line BIP-24/8 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LBE[19:0] Bits LBE[19:0] represent the number of line BIP-24/8 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to any of the RLOP Line BIP-24/8 Register or Line FEBE Register addresses. Such a write transfers the internally accumulated error count to the Line BIP-24/8 Registers within approximately 2 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R Type Function Unused Unused Unused Unused LBE[19] LBE[18] LBE[17] LBE[16] Default X X X X X X X X
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Register 0x1D: RLOP Line FEBE LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LFE[7] LFE[6] LFE[5] LFE[4] LFE[3] LFE[2] LFE[1] LFE[0] Default X X X X X X X X
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Register 0x1E: RLOP Line FEBE Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LFE[15] LFE[14] LFE[13] LFE[12] LFE[11] LFE[10] LFE[9] LFE[8] Default X X X X X X X X
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Register 0x1F: RLOP Line FEBE MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LFE[19:0] Bits LFE[19:0] represent the number of line FEBE errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to any of the RLOP Line BIP-24/8 Register or Line FEBE Register addresses. Such a write transfers the internally accumulated error count to the Line FEBE Registers within approximately 2 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R Type Function Unused Unused Unused Unused LFE[19] LFE[18] LFE[17] LFE[16] Default X X X X X X X X
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Register 0x20: TLOP Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LRDI: The LRDI bit controls the insertion of line remote defect indication (LRDI). When LRDI is a logic one, the S/UNI-PLUS inserts line RDI into the transmit stream. Line RDI is inserted by transmitting the code 110 in bit positions 6, 7, and 8 of the K2 byte of the transmit stream. The LRDI bit is logically ORed with the external TLRDI input. APSREG: The APSREG bit selects the source for the transmit APS channel. When APSREG is a logic zero, 0x0000 hexadecimal is inserted in the transmit APS channel. When APSREG is a logic one, the transmit APS channel is inserted from the TLOP Transmit K1 Register and the TLOP Transmit K2 Register. The APS bytes may also be inserted using the TTOHEN and TTOH inputs. Values inserted using the TTOHEN input take precedence over the source selected by the APSREG bit. Reserved: The reserved bits must be programmed to logic zero for proper operation. R/W R/W R/W R/W R/W R/W R/W Type Function Unused Reserved APSREG Reserved Reserved Reserved Reserved LRDI Default X 0 0 0 0 0 0 0
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Register 0x21: TLOP Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBIP24/8: The DBIP24/8 bit controls the insertion of bit errors continuously in the B2 byte(s). When DBIP24/8 is a logic one, the B2 byte(s) are inverted. R/W Type Function Unused Unused Unused Unused Unused Unused Unused DBIP24/8 Default X X X X X X X 0
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Register 0x22: TLOP Transmit K1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K1[7:0]: The K1[7:0] bits contain the value inserted in the K1 byte when the APSREG bit in the TLOP Control Register is a logic one. K1[7] is the most significant bit, corresponding to the first bit (bit 1) transmitted. K1[0] is the least significant bit, corresponding to the last bit (bit 8) transmitted. The bits in this register are double buffered so that register writes do not need to be synchronized to SONET/SDH frame boundaries. The insertion of a new APS code value is initiated by a write to this register. The contents of this register, and the TLOP Transmit K2 Register are inserted in the transmit stream starting at the next frame boundary. Successive writes to this register must be spaced at least two frames (250 s) apart. Type R/W R/W R/W R/W R/W R/W R/W R/W Function K1[7] K1[6] K1[5] K1[4] K1[3] K1[2] K1[1] K1[0] Default 0 0 0 0 0 0 0 0
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Register 0x23: TLOP Transmit K2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 K2[7:0]: The K2[7:0] bits contain the value inserted in the K2 byte when the APSREG bit in the TLOP Control Register is a logic one. K2[7] is the most significant bit, corresponding to the first bit (bit 1) transmitted. K2[0] is the least significant bit, corresponding to the last bit (bit 8) transmitted. The bits in this register are double buffered so that register writes do not need to be synchronized to SONET/SDH frame boundaries. The insertion of a new APS code value is initiated by a write to the TLOP Transmit K1 Register. A coherent APS code value is ensured by writing the desired K2 APS code value to this register before writing the TLOP Transmit K1 Register. Type R/W R/W R/W R/W R/W R/W R/W R/W Function K2[7] K2[6] K2[5] K2[4] K2[3] K2[2] K2[1] K2[0] Default 0 0 0 0 0 0 0 0
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Register 0x28: SSTB Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused RRAMACC Reserved Reserved PER5 TNULL NOSYNC LEN16 Default X 0 0 0 0 1 0 0
This register controls the receive and transmit portions of the SSTB. LEN16: The LEN16 bit selects the length of the section trace message to be 16 bytes or 64 bytes. When LEN16 is a logic one, a 16 byte section trace message is selected. When LEN16 is a logic zero, a 64 byte section trace message is selected. NOSYNC: The NOSYNC bit disables the writing of the section trace message into the trace buffer to be synchronized to the content of the message. When LEN16 is a logic one and NOSYNC is a logic zero, the receive section trace message byte with its most significant bit set will be written to the first location in the buffer. When LEN16 and NOSYNC are logic zero, the byte after the carriage return/linefeed (CR/LF) sequence will be written to the first location in the buffer. When NOSYNC is a logic one, synchronization is disabled, and the section trace message buffer behaves as a circular buffer. TNULL: The TNULL bit controls the insertion of an all-zero section trace identifier message in the transmit stream. When TNULL is a logic one, the contents of the transmit buffer is ignored and all-zeros bytes are inserted. When TNULL is a logic zero, the contents of the transmit section trace buffer is sent to TSOP for insertion into the J0 transmit section overhead byte. TNULL should
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be set high before changing the contents of the trace buffer to avoid sending partial messages. PER5: The PER5 bit controls the number of times a section trace identifier message must be received unchanged before being accepted. When PER5 is a logic one, a message is accepted when it is received unchanged five times consecutively. When PER5 is a logic zero, the message is accepted after three identical repetitions. RRAMACC: The RRAMACC bit directs read and writes access to either the receive or transmit section trace buffer. When RRAMACC is a logic one, microprocessor accesses are directed to the receive section trace buffer. When RRAMACC is a logic zero, microprocessor accesses are directed to the transmit section trace buffer. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x29: SSTB Section Trace Identifier Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R Function BUSY Unused Unused Unused Unused Unused Unused Unused Default 0 X X X X X X X
This register reports the section trace identifier status of the SSTB. BUSY: The BUSY bit reports whether a previously initiated indirect read or write to a message buffer has been completed. BUSY is set to a logic one immediately upon writing to the SSTB Indirect Address register, and stays high until the initiated access is completed (about 0.6 s in STS-3 or 1.8 s in STS-1). This register should be polled to determine when new data is available in the SSTB Indirect Data register.
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Register 0x2A: SSTB Indirect Address Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0] Default 0 0 0 0 0 0 0 0
This register supplies the address used to index into section trace identifier buffers. A[6:0]: The indirect read address bits (A[6:0]) are used to address the section trace identifier buffers. When RRAMACC is set high, addresses 0 to 63 reference the captured message page while addresses 64 to 127 reference the expected message page of the receive section trace buffer. The captured message page contains the identifier bytes extracted from the receive stream. The expected message page contains the section trace message to which the captured message page is compared. When RRAMACC is set low, addresses 0 to 63 reference the transmit section trace buffer which contains the section trace message inserted in the transmit stream. RWB: The access control bit (RWB) selects between an indirect read or write access to the selected section trace buffer (receive or transmit as determined by the RRAMACC bit). Writing to this register initiates an access to the selected section trace buffer. When RWB is a logic one, a read access is initiated. The addressed location's contents are placed in the SSTB Indirect Data register. When RWB is a logic zero, a write access is initiated. The data in the SSTB Indirect Data register is written to the addressed location in the selected buffer.
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Register 0x2B: SSTB Indirect Data Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default 0 0 0 0 0 0 0 0
This register contains the data read from the section trace message buffer after a read operation or the data to be written into the buffer before a write operation. D[7:0]: The indirect data bits (D[7:0]) contains the data read from either the transmit or receive section trace buffer after an indirect read operation is completed. The data that is written to a buffer is set up in this register before initiating the indirect write operation.
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Register 0x30: RPOP Status/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R/W R Type R/W Function Reserved Unused LOPV Unused PAISV PRDIV NEWPTRI NEWPTRE Default 0 X X X X X X 0
This register allows the status of path level alarms to be monitored. NEWPTRE: The NEWPTRE bit is the interrupt enable for the receive new pointer status. When NEWPTRE is a logic one, an interrupt is generated when the pointer interpreter validates a new pointer. NEWPTRI: The NEWPTRI bit is the receive new pointer interrupt status bit. NEWPTRI is a logic one when the pointer interpreter has validated a new pointer value (H1, H2). NEWPTRI is cleared when this register is read. PRDIV: The PRDIV bit is read to determine the remote defect indication state. When PRDIV is a logic one, the S/UNI-PLUS has declared path RDI. PAISV: The PAISV bit is read to determine the path AIS state. When PAISV is a logic one, the S/UNI-PLUS has declared path AIS. PLOPV: The PLOPV bit is read to determine the loss of pointer state. When PLOPV is a logic one, the S/UNI-PLUS has declared LOP .
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Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x31: RPOP Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R Type R Function PSLI Unused LOPI Unused PAISI PRDII BIPEI FEBEI Default X X X X X X X X
This register allows identification and acknowledgment of path level alarm and error event interrupts. FEBEI: The FEBEI bit is the path FEBE interrupt status bit. FEBEI is a logic one when a FEBE error is detected. This bit is cleared when this register is read. BIPEI: The BIPEI bit is the path BIP-8 interrupt status bit. BIPEI is a logic one when a B3 error is detected. This bit is cleared when this register is read. PRDII: The PRDII bit is the path remote defect indication interrupt status bit. PRDII is a logic one when a change in the path RDI state or the auxiliary path RDI state occurs. This bit is cleared when this register is read. PAISI: The PAISI bit is the path alarm indication signal interrupt status bit. PAISI is a logic one when a change in the path AIS state occurs. This bit is cleared when this register is read.
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LOPI: The LOPI bit is the loss of pointer interrupt status bit. LOPI is a logic one when a change in the LOP state occurs. This bit is cleared when this register is read. PSLI: The PSLI bit is the change of path signal label interrupt status bit. PSLI is a logic one when a change is detected in the path signal label register. The current path signal label can be read from the RPOP Path Signal Label register. This bit is cleared when this register is read.
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Register 0x32: RPOP Pointer Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R Type R Function ILLJREQI Unused DISCOPAI INVNDFI ILLPTRI NSEI PSEI NDFI Default X X X X X X X X
This register allows identification and acknowledgment of pointer event interrupts. NDFI: The NDFI bit is the new data flag interrupt status bit. NDFI is a logic one when the NDF field is active in the received pointer (H1, H2). This bit is cleared when this register is read. PSEI: The PSEI bit is the positive stuff event interrupt status bit. PSEI is a logic one when a positive stuff event is detected in the received pointer (H1, H2). This bit is cleared when this register is read. NSEI: The NSEI bit is the negative stuff event interrupt status bit. NSEI is a logic one when a negative stuff event is detected in the received pointer (H1, H2). This bit is cleared when this register is read. ILLPTRI: The ILLPTRI bit is the illegal pointer interrupt status bit. ILLPTRI is a logic one when an illegal pointer value is detected. This bit is cleared when this register is read.
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INVNDFI: The INVNDFI bit is the illegal new data field value interrupt status bit. INVNDFI is a logic one when an illegal NDF field value is detected in the receive payload pointer. An illegal NDF field is any one of the following six values: 0x0, 0x3, 0x5, 0xA, 0xC, and 0xF. This bit is cleared when this register is read. DISCOPAI: The DISCOPAI bit is the discontinuous change of pointer interrupt status bit. DISCOPAI is a logic one when a new pointer value is validated without an accompanying NDF indication. This bit is cleared when this register is read. ILLJREQI: The ILLJREQI bit is the illegal justification request interrupt status bit. ILLJREQI is a logic one when the pointer interpreter detects an illegal pointer justification request event. This bit is cleared when this register is read.
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Register 0x33: RPOP Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PSLE Reserved LOPE Reserved PAISE PRDIE BIPEE FEBEE Default 0 0 0 0 0 0 0 0
This register allows interrupt generation to be enabled for path level alarm and error events. FEBEE: The FEBEE bit is the interrupt enable for path FEBEs. When FEBEE is a logic one, an interrupt is generated when a path FEBE is detected. BIPEE: The BIPEE bit is the interrupt enable for path BIP-8 errors. When BIPEE is a logic one, an interrupt is generated when a B3 error is detected. PRDIE: The PRDIE bit is the interrupt enable for path RDI. When PRDIE is a logic one, an interrupt is generated when the path RDI state changes. PAISE: The PAISE bit is the interrupt enable for path AIS. When PAISE is a logic one, an interrupt is generated when the path AIS state changes. LOPE: The LOPE bit is the interrupt enable for LOP When LOPE is a logic one, an . interrupt is generated when the LOP state changes.
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PSLE: The PSLE bit is the interrupt enable for changes in the received path signal label. When PSLE is a logic one, an interrupt is generated when the received C2 byte changes. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x34: RPOP Pointer Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function ILLJREQE Reserved DISCOPAE INVNDFE ILLPTRE NSEE PSEE NDFE Default 0 0 0 0 0 0 0 0
This register is used to enable pointer event interrupts. NDFE: The NDFE bit is the interrupt enable for NDF events. When NDFE is a logic one, an interrupt is generated when an NDF event is detected. PSEE: The PSEE bit is the interrupt enable for positive stuff events. When PSEE is a logic one, an interrupt is generated when a positive stuff event is detected. NSEE: The NSEE bit is the interrupt enable for negative stuff events. When NSEE is a logic one, an interrupt is generated when a negative stuff event is detected. ILLPTRE: The ILLPTRE bit is the interrupt enable for illegal pointers. When ILLPTRE is a logic one, an interrupt is generated when an illegal pointer is detected. INVNDFE: The INVNDFE bit is the interrupt enable for invalid new data flags. When INVNDFE is a logic one, an interrupt is generated when an invalid NDF is detected.
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DISCOPAE: The DISCOPAE bit is the interrupt enable for discontinuous pointer change events. When DISCOPAE is a logic one, an interrupt is generated when a discontinuous pointer change is detected. ILLJREQE: The ILLJREQE bit is the interrupt enable for illegal pointer justification events. When ILLJREQE is a logic one, an interrupt is generated when an illegal justification request is detected. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x35: RPOP Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTR[7:0]: The PTR[7:0] bits contain the eight LSBs of the current pointer value that is interpreted from the H1 and H2 bytes. The NDFI, NSEI and PSEI bits of the RPOP Pointer Interrupt Status register should be read before and after reading this register to ensure that the pointer value did not change during the register read. Type R R R R R R R R Function PTR[7] PTR[6] PTR[5] PTR[4] PTR[3] PTR[2] PTR[1] PTR[0] Default X X X X X X X X
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Register 0x36: RPOP Pointer MSB and RDI Filter Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTR[9:8]: The PTR[9:8] bits contain the two MSBs of the current pointer value that is interpreted from the H1 and H2 bytes. The NDFI, NSEI and PSEI bits of the RPOP Pointer Interrupt Status register should be read before and after reading this register to ensure that the pointer value did not change during the register read. S0, S1: The S0 and S1 bits contain the two S bits received in the last H1 byte. These bits should be software debounced by reading this register at least twice. RDI10: The RDI10 bit controls the filtering of the remote defect indication and the auxiliary remote defect indication. When RDI10 is a logic one, the PRDI and APRDI status is updated when the same value is received in the corresponding bit of the G1 byte for ten consecutive frames. When RDI10 is a logic zero, the PRDI and APRDI status is updated when the same value is received for five consecutive frames. R R R R R/W Type Function Unused Unused RDI10 Unused S1 S0 PTR[9] PTR[8] Default X X 0 X X X X X
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Register 0x37: RPOP Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PSL[7:0]: The PSL[7:0] bits contain the path signal label byte (C2). The value in this register is updated to a new path signal label value if the same new value is observed for two consecutive frames. Type R R R R R R R R Function PSL[7] PSL[6] PSL[5] PSL[4] PSL[3] PSL[2] PSL[1] PSL[0] Default X X X X X X X X
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Register 0x38: RPOP Path BIP-8 LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PBE[7] PBE[6] PBE[5] PBE[4] PBE[3] PBE[2] PBE[1] PBE[0] Default X X X X X X X X
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Register 0x39: RPOP Path BIP-8 MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PBE[15:0]: PBE[15:0] represent the number of B3 errors (individual or block) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RPOP Path BIP-8 Register addresses or to either of the RPOP Path FEBE Register addresses. Such a write transfers the internally accumulated error count to the Path BIP-8 registers within a maximum of 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. Type R R R R R R R R Function PBE[15] PBE[14] PBE[13] PBE[12] PBE[11] PBE[10] PBE[9] PBE[8] Default X X X X X X X X
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Register 0x3A: RPOP Path FEBE LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PFE[7] PFE[6] PFE[5] PFE[4] PFE[3] PFE[2] PFE[1] PFE[0] Default X X X X X X X X
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Register 0x3B: RPOP Path FEBE MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PFE[15] PFE[14] PFE[13] PFE[12] PFE[11] PFE[10] PFE[9] PFE[8] Default X X X X X X X X
These registers allow path FEBEs to be accumulated. PFE[15:0]: PFE[15:0] represent the number of path FEBE errors (G1) that have been detected since the last time the error count was polled. The error count is polled by writing to either of the RPOP Path BIP-8 Register addresses or to either of the RPOP Path FEBE Register addresses. Such a write transfers the internally accumulated error count to the Path FEBE Registers within a maximum of 7 s and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that ensures that coincident events are not lost. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks.
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Register 0x3C: RPOP Auxiliary RDI Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 APRDIE: The APRDIE bit is the interrupt enable for auxiliary path RDI. When APRDIE is a logic one, an interrupt is generated when the auxiliary path RDI state changes. APRDIV: The APRDIV bit is read to determine the auxiliary path RDI state. When APRDIV is a logic one, the S/UNI-PLUS has declared auxiliary path RDI. BLKFEBE: The BLKFEBE bit controls the accumulation of path FEBE events. When BLKFEBE is a logic one, a single FEBE is accumulated if the received FEBE code indicates between one and eight B3 errors have been detected by the far end. When BLKFEBE is a logic zero, the literal number of FEBEs is accumulated. Reserved: The reserved bits must be programmed to logic zero for proper operation. R/W R/W R R/W R/W Type Function Unused Unused Reserved BLKFEBE Unused Reserved APRDIE APRDIV Default X X 0 0 X 0 0 X
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Register 0x3D: RPOP Error Event Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function SOS ENSS BLKBIP DISFS BLKBIPO Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0
This register contains error event control bits. BLKBIPO: When BLKBIPO is a logic one, path FEBE indications are generated on a block basis. A single FEBE is transmitted if one or more path B3 error indications are detected per frame. When BLKBIPO is a logic zero, the transmitted FEBE indicates the number of B3 errors detected (between 0 and 8 errors per frame). DISFS: When DISFS is a logic one, the B3 calculation ignores the fixed stuff columns in an AU-3 carrying a VC-3. When DISFS is a logic zero, the B3 calculation includes the fixed stuff columns in an STS-1 stream. This bit is ignored when the S/UNI-PLUS is processing an STS-3c (STM-1) stream. BLKBIP: When BLKBIP is a logic one, B3 errors are reported and accumulated on a block basis. A single B3 error is accumulated and reported to the TPOP if one or more B3 errors are detected per frame. When BLKBIP is a logic zero, each B3 error is accumulated and reported. ENSS: The ENSS bit controls whether the SS bits in the payload pointer are included in the pointer interpreter state machine. When ENSS is a logic one, an
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incorrect SS bit pattern causes the pointer interpreter to enter the LOP (loss of pointer) state and prevents a new pointer indication. When ENSS is a logic zero, the SS bits are ignored by the pointer interpreter. SOS: The SOS controls the spacing between consecutive pointer justification events in the receive stream. When SOS is a logic one, the definition of inc_ind and dec_ind indications (from Figure 4) includes the requirement that active offset changes have occurred at least three frames ago. When SOS is a logic zero, pointer justification indications in the receive stream are followed without regard to the proximity of previous active offset changes. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x40: TPOP Control/Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W Function Reserved Unused Unused Unused EXCFS Reserved DBIP8 PAIS Default 0 X X X 0 0 0 0
This register allows insertion of path level alarms and diagnostic signals. PAIS: The PAIS bit controls the insertion of STS path alarm indication signal. This register bit value is logically ORed with the input TPAIS. When a logic one is written to this bit position, the complete SPE, and the pointer bytes (H1, H2, and H3) are overwritten with the all-ones pattern. When a logic zero is written to this bit position, the pointer bytes and the SPE are processed normally. DBIP8: The DBIP8 bit controls the insertion of bit errors continuously in the B3 byte. When DBIP8 is a logic one, the B3 byte is inverted. EXCFS: The EXCFS bit controls the inclusion of bytes in the fixed stuff columns of the STS-1/AU-3 payload in B3 calculations. When EXCFS is a logic one, the contents of the bytes in columns 30 and 59 do not affect the value of the B3 byte. When EXCFS is a logic zero, the fixed stuff bytes are included in the B3 calculations. This bit is only active if the S/UNI-PLUS is transmitting an STS-1 stream. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x41: TPOP Pointer Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused FTPTR SOS PLD NDF NSE PSE Reserved Default X 0 0 0 0 0 0 0
This register allows control over the transmitted payload pointer for diagnostic purposes. PSE: The PSE bit controls the insertion of positive pointer movements. A logic zero to logic one transition on this bit enables the insertion of a single positive pointer justification in the transmit stream. This register bit is automatically cleared when the pointer movement is inserted. NSE: The NSE bit controls the insertion of negative pointer movements. A logic zero to logic one transition on this bit enables the insertion of a single negative pointer justification in the transmit stream. This register bit is automatically cleared when the pointer movement is inserted. NDF: The NDF bit controls the insertion of new data flags in the inserted payload pointer. When a logic one is written to this bit position, the pattern contained in the NDF[3:0] bit positions in the TPOP Arbitrary Pointer MSB Register is inserted continuously in the payload pointer. When a logic zero is written to this bit position, the normal pattern (0110) is inserted in the payload pointer.
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PLD: The PLD bit controls the loading of the pointer value contained in the TPOP Arbitrary Pointer Registers. Normally the TPOP Arbitrary Pointer Registers are written to set up the arbitrary new pointer value, the S-bit values, and the NDF pattern. A logic one is then written to this bit position to load the new pointer value. The new data flag bit positions are set to the programmed NDF pattern for the first frame; subsequent frames have the new data flag bit positions set to the normal pattern (0110) unless the NDF bit described above is set to a logic one. This bit is automatically cleared after the new payload pointer has been loaded. Note: When loading an out of range pointer (that is a pointer with a value greater than 782), the TPOP continues to operate with timing based on the last valid pointer value. The out of range pointer value is inserted in the transmit stream. Although a valid SPE will continue to be generated, it is unlikely to be extracted by downstream circuitry which should be in a loss of pointer state. SOS: The SOS bit controls the stuff opportunity spacing between consecutive SPE positive or negative stuff events. When SOS is a logic zero, stuff events may be generated every frame as controlled by the PSE and NSE register bits described above. When SOS is a logic one, stuff events may be generated at a maximum rate of once every four frames. FTPTR: The force transient pointer bit (FTPTR) enables the insertion of the pointer value contained in the Arbitrary Pointer Registers into the transmit stream for diagnostic purposes. When FTPTR is a logic one, the APTR[9:0] bits of the Arbitrary Pointer Registers are inserted into the H1 and H2 bytes of the transmit stream. At least one corrupted pointer is guaranteed to be sent. When FTPTR is a logic zero, the pointer value in the Current Pointer registers is inserted in the transmit stream. Reserved: The reserved bits must be programmed to logic zero for proper operation.
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Register 0x43: TPOP Current Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTR[7:0]: The CPTR[7:0] bits, along with the CPTR[9:8] bits in the TPOP Current Pointer MSB Register reflect the value of the current payload pointer being inserted in the transmit stream. The value may be changed by loading a new pointer value using the TPOP Arbitrary Pointer LSB and MSB Registers, or by inserting positive and negative pointer movements using the PSE and NSE register bits. Type R R R R R R R R Function CPTR[7] CPTR[6] CPTR[5] CPTR[4] CPTR[3] CPTR[2] CPTR[1] CPTR[0] Default X X X X X X X X
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Register 0x44: TPOP Current Pointer MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPTR[9:8]: The CPTR[9:8] bits, along with the CPTR[7:0] bits in the TPOP Current Pointer LSB Register reflect the value of the current payload pointer being inserted in the transmit stream. The value may be changed by loading a new pointer value using the TPOP Arbitrary Pointer LSB and MSB Registers, or by inserting positive and negative pointer movements using the PSE and NSE register bits. It is recommended the CPTR[9:0] value be software debounced to ensure a correct value is received. R R Type Function Unused Unused Unused Unused Unused Unused CPTR[9] CPTR[8] Default X X X X X X X X
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Register 0x45: TPOP Arbitrary Pointer LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function APTR[7] APTR[6] APTR[5] APTR[4] APTR[3] APTR[2] APTR[1] APTR[0] Default 0 0 0 0 0 0 0 0
This register allows an arbitrary pointer to be inserted for diagnostic purposes. APTR[7:0]: The APTR[7:0] bits, along with the APTR[9:8] bits in the TPOP Arbitrary Pointer MSB Register are used to set an arbitrary payload pointer value. The arbitrary pointer value is inserted in the transmit stream by writing a logic one to the PLD bit in the TPOP Pointer Control Register. If the FTPTR bit in the TPOP Pointer Control register is a logic one, the current APTR[9:0] value is inserted into the payload pointer bytes (H1 and H2) in the transmit stream.
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Register 0x46: TPOP Arbitrary Pointer MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function NDF[3] NDF[2] NDF[1] NDF[0] S[1] S[0] APTR[9] APTR[8] Default 1 0 0 1 0 0 0 0
This register allows an arbitrary pointer to be inserted for diagnostic purposes. APTR[9:8]: The APTR[9:8] bits, along with the APTR[7:0] bits in the TPOP Arbitrary Pointer LSB Register are used to set an arbitrary payload pointer value. The arbitrary pointer value is inserted in the transmit stream by writing a logic one to the PLD bit in the TPOP Pointer Control Register. If the FTPTR bit in the TPOP Pointer Control register is a logic one, the current APTR[9:0] value is inserted into the payload pointer bytes (H1 and H2) in the transmit stream. S[1], S[0]: The S[1:0] bits contain the value inserted in the S[1:0] bit positions (also referred to as the unused bits) in the payload pointer. NDF[3:0]: The NDF[3:0] bits contain the value inserted in the NDF bit positions when an arbitrary new payload pointer value is inserted (using the PLD bit in the TPOP Pointer Control Register) or when new data flag generation is enabled using primary input NDF, or the NDF bit in the TPOP Pointer Control Register.
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Register 0x47: TPOP Path Trace Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function J1[7] J1[6] J1[5] J1[4] J1[3] J1[2] J1[1] J1[0] Default 0 0 0 0 0 0 0 0
This register allows control over the path trace byte. J1[7:0]: The J1[7:0] bits are inserted in the J1 byte position in the transmit stream when insertion from the transmit path overhead port is disabled, and insertion from the SPTB is disabled.
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Register 0x48: TPOP Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function C2[7] C2[6] C2[5] C2[4] C2[3] C2[2] C2[1] C2[0] Default 0 0 0 1 0 0 1 1
This register allows control over the path signal label. Upon reset the register defaults to 13H, which signifies an equipped ATM payload. C2[7:0]: The C2[7:0] bits are inserted in the C2 byte position in the transmit stream when insertion from the transmit path overhead port is disabled.
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Register 0x49: TPOP Path Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function FEBE[3] FEBE[2] FEBE[1] FEBE[0] PRDI APRDI G1[1] G1[0] Default 0 0 0 0 0 0 0 0
This register allows control over the path status byte. G1[1], G1[0]: The G1[1:0] bits are inserted in the unused bit positions in the path status byte when the SRCG1 bit of the TPOP Source Control Register is logic zero and primary input TPOHEN is low during the unused bit positions in the path overhead input stream, TPOH. APRDI: The APRDI bit controls the insertion of the auxiliary path remote defect indication. When APRDI is a logic one, the APRDI bit position in the path status byte is set high. When APRDI is a logic zero, the APRDI bit position in the path status byte is set low. This bit has no effect if the SRCG1 bit of the TPOP Source Control Register is logic one or primary input TPOHEN is high during the path status remote defect indication bit position in the path overhead input stream in which case the value is inserted from TPOH. PRDI: The PRDI bit controls the insertion of the path remote defect indication. This register bit value is logically ORed with the input TPRDI. When PRDI is a logic one, the PRDI bit position in the path status byte is set high. When PRDI is a logic zero, the PRDI bit position in the path status byte is set low. This bit has no effect if the SRCG1 bit of the TPOP Source Control Register is logic one or primary input TPOHEN is high during the path status remote
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defect indication bit position in the path overhead input stream in which case the value is inserted from TPOH. FEBE[3:0]: The FEBE[3:0] bits are inserted in the FEBE bit positions in the path status byte when the SRCG1 bit of the TPOP Source Control Register is logic zero and primary input TPOHEN is low during the path status FEBE bit positions in the path overhead input stream, TPOH. The value contained in FEBE[3:0] is cleared after being inserted in the path status byte. Any non-zero FEBE value overwrites the value that would normally have been inserted based on the number of receive B3 errors during the last frame. When reading this register, a non-zero value in these bit positions indicates that the insertion of this value is still pending.
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Register 0x4A: TPOP Path User Channel Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function F2[7] F2[6] F2[5] F2[4] F2[3] F2[2] F2[1] F2[0] Default 0 0 0 0 0 0 0 0
This register allows control over the path user channel. F2[7:0]: The F2[7:0] bits are inserted in the F2 byte position in the transmit stream when insertion from the transmit path overhead port is disabled.
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Register 0x4B: TPOP Path Growth #1 (Z3) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Z3[7] Z3[6] Z3[5] Z3[4] Z3[3] Z3[2] Z3[1] Z3[0] Default 0 0 0 0 0 0 0 0
This register allows control over path growth byte #1 (Z3). Z3[7:0]: The Z3[7:0] bits are inserted in the Z3 byte position in the transmit stream when insertion from the transmit path overhead port is disabled.
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Register 0x4C: TPOP Path Growth #2 (Z4) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Z4[7] Z4[6] Z4[5] Z4[4] Z4[3] Z4[2] Z4[1] Z4[0] Default 0 0 0 0 0 0 0 0
This register allows control over path growth byte #2 (Z4). Z4[7:0]: The Z4[7:0] bits are inserted in the Z4 byte position in the transmit stream when insertion from the transmit path overhead port is disabled.
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Register 0x4D: TPOP Path Growth #3 (Z5) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function Z5[7] Z5[6] Z5[5] Z5[4] Z5[3] Z5[2] Z5[1] Z5[0] Default 0 0 0 0 0 0 0 0
This register allows control over path growth byte #3 (Z5). Z5[7:0]: The Z5[7:0] bits are inserted in the Z5 byte position in the transmit stream when insertion from the transmit path overhead port is disabled.
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Register 0x50: RACP Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the four cell receive FIFO. When FIFORST is a logic zero, the FIFO operates normally. When FIFORST is a logic one, the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until FIFORST is cleared. DDSCR: The DDSCR bit controls the descrambling of the cell payload. When DDSCR is a logic one, cell payload descrambling is disabled. When DDSCR is a logic zero, payload descrambling is enabled. HCSADD: The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HCS octet prior to comparison. When HCSADD is a logic one, the polynomial is added, and the resulting HCS is compared. When HCSADD is a logic zero, the polynomial is not added, and the unmodified HCS is compared. HCSADD can also be used to force the S/UNI-PLUS out of cell delineation. HCSPASS: The HCSPASS bit controls the dropping of cells based on the detection of an HCS error. When HCSPASS is a logic zero, cells are dropped based on the criteria of the HCS verification state machine. When HCSPASS is a logic one, Type R/W R/W R/W R/W R/W R/W R/W R/W Function FSEN RXPTYPE PASS DISCOR HCSPASS HCSADD DDSCR FIFORST Default 1 0 0 0 0 1 0 0
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cells are passed to the receive FIFO regardless of errors detected in the HCS, and the HCS verification finite state machine never exits the correction mode. Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states. DISCOR: The DISCOR bit disables the HCS error correction algorithm. When DISCOR is a logic zero, the error correction algorithm is enabled, and single-bit errors detected in the cell header are corrected. When DISCOR is a logic one, the error correction algorithm is disabled, and any error detected in the cell header is treated as an uncorrectable HCS error. PASS: The PASS bit controls the function of the cell filter. When PASS is a logic zero, cells which match the header cell filter and which have VPI and VCI fields set to 0 are dropped. When PASS is a logic one, the match header pattern registers are ignored and filtering of cells with VPI and VCI fields set to 0 is not performed. The default state of this bit together with the default states of the bits in the Match Mask and Match Pattern registers enable the dropping of cells containing all zero VCI and VPI fields. RXPTYPE: The RXPTYPE bit selects even or odd parity for outputs RXPRTY[1:0]. When RXPTYPE is a logic one, even parity is calculated for the output data on RDAT[15:0]; conversely, when RXPTYPE is a logic zero, odd parity is calculated for the output data. When RXPTYPE is set to logic one in word parity mode, output RXPRTY[1] is the even parity bit for outputs RDAT[15:0]. When RXPTYPE is set to logic zero in word parity mode, output RXPRTY[1] is the odd parity bit for outputs RDAT[15:0]. In word parity mode, RXPRTY[0] is held low. When RXPTYPE is set to logic one in byte parity mode, output RXPRTY[1] is the even parity bit for outputs RDAT[15:8] and output RXPRTY[0] is the even parity bit for outputs RDAT[7:0]. When RXPTYPE is a logic zero in byte parity mode, output RXPRTY[1] is the odd parity bit for outputs RDAT[15:8] and output RXPRTY[0] is the odd parity bit for outputs RDAT[7:0]. FSEN: The FSEN bit determines the payload mapping of ATM cells when STS-1 (AU-3) mapping is selected. When FSEN is set to logic one, the S/UNI-PLUS
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does not insert ATM cells into the two fixed stuff columns in the SPE. When FSEN is set to logic zero, the S/UNI-PLUS inserts cells into the entire SPE.
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Register 0x51: RACP Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FOVRI: The FOVRI bit is the FIFO overrun interrupt status bit. FOVRI is a logic one when a FIFO overrun occurs. This bit is cleared when this register is read. UHCSI: The UHCSI bit is the uncorrectable HCS error interrupt status bit. UHCSI is a logic one when an uncorrectable HCS error is detected. This bit is cleared when this register is read. CHCSI: The CHCSI bit is the correctable HCS error interrupt status bit. CHCSI is a logic one when a correctable HCS error is detected. This bit is cleared when this register is read. LCDI: The LCDI bit is the loss of cell delineation interrupt status bit. LCDI is a logic one when a change in the LCD state occurs. This bit is cleared when this register is read. OCDI: The OCDI bit is the out of cell delineation interrupt status bit. OCDI is a logic one when a change in the OCD state occurs. This bit is cleared when this register is read. Type R R R R R R R Function OCDV LCDV OCDI LCDI CHCSI UHCSI FOVRI Unused Default X X X X X X X X
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LCDV: The LCDV bit indicates the loss of cell delineation state. Loss of cell delineation is declared (LCDV is a logic one) when out of cell delineation persists for 4 ms or more. Loss of cell delineation is removed (LCDV is a logic zero) when out of cell delineation is absent for 4 ms. OCDV: The OCDV bit indicates the out of cell delineation state. When OCDV is a logic one, the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states, and is hunting for the cell boundaries in the synchronous payload envelope. When OCDV is a logic zero, the cell delineation state machine is in the 'SYNC' state and cells are passed through the receive FIFO. The cell delineation state machine transitions from the SYNC state to the HUNT state immediately when either loss of signal (LOS), loss of frame (LOF), loss of pointer (LOP), line AIS or path AIS is declared or when seven consecutive cells with incorrect HCS's are detected. The cell delineation state machine remains in HUNT state as long as one of the above alarms is active or if cells with a correct HCS cannot be found.
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Register 0x52: RACP Interrupt Enable/Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function OCDE LCDE HCSE FIFOE LCDDROP RCALEVEL0 HCSFTR[1] HCSFTR[0] Default 0 0 0 0 0 1 0 0
HCSFTR[1:0]: The HCS filter bits, HCSFTR[1:0], indicate the number of error free cells required while in detection mode before reverting back to correction mode. Please refer to Figure 6 for details. Table 2 Cell Acceptance Threshold One ATM cell with correct HCS before resumption of cell correction. Two ATM cells with correct HCS before resumption of cell correction. Four ATM cells with correct HCS before resumption of cell correction. Eight ATM cells with correct HCS before resumption of cell correction.
HCSFTR[1:0] 00 01 10 11
RCALEVEL0: The RCALEVEL0 bit controls the function of the RCA output. When RCALEVEL0 is a logic one, a high to low transition on output RCA indicates that the receive FIFO is empty. When RCALEVEL0 is a logic zero, a high to low transition on output RCA indicates that the receive FIFO is almost empty
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and contains only four words. Refer to the Drop Side Receive Interface timing diagrams in the Functional Timing section. LCDDROP: The LCD drop bit, LCDDROP enables the dropping of cells while in the loss , of cell delineation state. When LCDDROP is set to logic one, received cells are not written into the FIFO until the LCD indication is deasserted, which occurs after being continuously in the SYNC state for 4 ms. If LCDDROP is set to logic zero, cells are written to the FIFO when in the SYNC state, regardless of the LCD state. FIFOE: The FIFOE bit is the interrupt enable for FIFO overruns. When FIFOE is a logic one, an interrupt is generated when the FIFO overruns. HCSE: The HCSE bit is the interrupt enable for HCS errors. When HCSE is a logic one, an interrupt is generated when an HCS error is detected. LCDE: The LCDE bit is the interrupt enable for loss of cell delineation. When LCDE is a logic one, an interrupt is generated when the LCD state changes. OCDE: The OCDE bit is the interrupt enable for out of cell delineation. When OCDE is a logic one, an interrupt is generated when the OCD state changes.
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Register 0x53: RACP Match Header Pattern Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GFC[3:0]: The GFC[3:0] bits contain the pattern to match in the first, second, third and fourth bits of the first octet of the 53 octet cell, in conjunction with the RACP Match Header Mask Register. The PASS bit in the RACP Control Register must be a logic zero to enable dropping of cells matching this pattern. Note that an all-zeros pattern must be present in the VPI and VCI fields of the idle or unassigned cell. PTI[2:0]: The PTI[2:0] bits contain the pattern to match in the fifth, sixth and seventh bits of the fourth octet of the 53 octet cell, in conjunction with the RACP Match Header Mask Register. The PASS bit in the RACP Control Register must be a logic zero to enable dropping of cells matching this pattern. CLP: The CLP bit contains the pattern to match in the eighth bit of the fourth octet of the 53 octet cell, in conjunction with the RACP Match Header Mask Register. The PASS bit in the RACP Control Register must be a logic zero to enable dropping of cells matching this pattern. Type R/W R/W R/W R/W R/W R/W R/W R/W Function GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP Default 0 0 0 0 0 0 0 0
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Register 0x54: RACP Match Header Mask Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MGFC[3:0]: The MGFC[3:0] bits contain the mask pattern for the first, second, third and fourth bits of the first octet of the 53 octet cell. This mask is applied to the RACP Match Header Pattern Register to select the bits included in the cell filter. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. A logic zero causes the masking of the corresponding bit. MPTI3:0]: The MPTI[3:0] bits contain the mask pattern for the fifth, sixth and seventh bits of the fourth octet of the 53 octet cell. This mask is applied to the RACP Match Header Pattern Register to select the bits included in the cell filter. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. A logic zero causes the masking of the corresponding bit. MCLP: The CLP bit contains the mask pattern for the eighth bit of the fourth octet of the 53 octet cell. This mask is applied to the RACP Match Header Pattern Register to select the bits included in the cell filter. A logic one in this bit position enables the MCLP bit in the pattern register to be compared. A logic zero causes the masking of the MCLP bit. Type R/W R/W R/W R/W R/W R/W R/W R/W Function MGFC[3] MGFC[2] MGFC[1] MGFC[0] MPTI2] MPTI[1] MPTI[0] MCLP Default 0 0 0 0 0 0 0 0
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Register 0x55: RACP Correctable HCS Error Count (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function CHCS[7] CHCS[6] CHCS[5] CHCS[4] CHCS[3] CHCS[2] CHCS[1] CHCS[0] Default X X X X X X X X
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Register 0x56: RACP Correctable HCS Error Count (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHCS[11:0]: The CHCS[11:0] bits indicate the number of correctable HCS error events that occurred during the last accumulation interval. The contents of these registers are valid 2 s after a transfer is triggered by a write to the receive cell count register space, the correctable HCS error count register space, or to the uncorrectable HCS error count register space. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R Type Function Unused Unused Unused Unused CHCS[11] CHCS[10] CHCS[9] CHCS[8] Default X X X X X X X X
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Register 0x57: RACP Uncorrectable HCS Error Count (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function UHCS[7] UHCS[6] UHCS[5] UHCS[4] UHCS[3] UHCS[2] UHCS[1] UHCS[0] Default X X X X X X X X
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Register 0x58: RACP Uncorrectable HCS Error Count (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UHCS[11:0]: The UHCS[11:0] bits indicate the number of uncorrectable HCS error events that occurred during the last accumulation interval. The contents of these registers are valid 2 s after a transfer is triggered by a write to the receive cell count register space, the correctable HCS error count register space, or to the uncorrectable HCS error count register space. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R Type Function Unused Unused Unused Unused UHCS[11] UHCS[10] UHCS[9] UHCS[8] Default X X X X X X X X
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Register 0x59: RACP Receive Cell Counter (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[7] RCELL[6] RCELL[5] RCELL[4] RCELL[3] RCELL[2] RCELL[1] RCELL[0] Default X X X X X X X X
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Register 0x5A: RACP Receive Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[15] RCELL[14] RCELL[13] RCELL[12] RCELL[11] RCELL[10] RCELL[9] RCELL[8] Default X X X X X X X X
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Register 0x5B: RACP Receive Cell Counter (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCELL[20:0]: The RCELL[20:0] bits indicate the number of cells received and written into the receive FIFO during the last accumulation interval. Cells received and filtered due to HCS errors or Idle/Unassigned cell matches are not counted. The counter should be polled every second to avoid saturation. The contents of these registers are valid 2 s after a transfer is triggered by a write to the receive cell count register space, the correctable HCS error count register space, or to the uncorrectable HCS error count register space. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R R Type Function Unused Unused Unused RCELL[20] RCELL[19] RCELL[18] RCELL[17] RCELL[16] Default X X X X X X X X
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Register 0x5C: RACP GFC Control and Miscellaneous Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RGFCE[3:0]: The RGFCE[3:0] bits are used to enable the GFC[3:0] bits serialized on output RGFC. For example, when RGFCE[3] is a logic one, the GFC[3] bit is output on RGFC. When RGFCE[3] is a logic zero, the GFC[3] bit is not output on RGFC. RXBYTEPRTY: The receive byte parity, RXBYTEPRTY, mode bit selects between byte and word parity mode for outputs RXPRTY[1:0]. When the RXBYTEPRTY bit is set to logic one, byte parity mode is selected; otherwise, word parity mode is selected. In byte parity mode, RXPRTY[1] is the parity bit for outputs RDAT[15:8], and RXPRTY[0] is the parity bit for outputs RDAT[7:0]. In word parity mode, RXPRTY[1] is the parity bit for outputs RDAT[15:0], and RXPRTY[0] is held low. Word parity mode can only be selected when the BUS8 input is low (i.e., the 16-bit FIFO interface is selected). CDDIS: The cell delineation disable bit, CDDIS, is used to defeat the cell delineation function. When the CDDIS bit is set to logic one, HCS errors are ignored, which makes every byte appear like a valid cell boundary. Ignoring HCS errors causes the cell delineation state machine to lock onto an arbitrary cell boundary and to enter and remain in the SYNC state. Once in the SYNC state, the incoming data is written to the FIFO. R/W R/W R/W R/W Type R/W R/W Function CDDIS RXBYTEPRTY Unused Unused RGFCE[3] RGFCE[2] RGFCE[1] RGFCE[0] Default 0 0 X X 1 1 1 1
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Register 0x60: TACP Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the four cell transmit FIFO. When FIFORST is a logic zero, the FIFO operates normally. When FIFORST is a logic one, the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until FIFORST is cleared. Idle/unassigned cells are transmitted until a subsequent cell is written to the transmit FIFO. DSCR: The DSCR bit controls the scrambling of the cell payload. When DSCR is a logic one, cell payload scrambling is disabled. When DSCR is a logic zero, payload scrambling is enabled. HCSADD: The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HCS octet prior to insertion in the transmit stream. When HCSADD is a logic one, the polynomial is added, and the resulting HCS is inserted. When HCSADD is a logic zero, the polynomial is not added, and the unmodified HCS is inserted. HCSADD takes effect unconditionally regardless of whether an idle/unassigned cell is being transmitted or whether the HCS octet has been read from the FIFO. Type R/W R R R/W R/W R/W R/W R/W Function FIFOE TSOCI FOVRI DHCS HCSB HCSADD DSCR FIFORST Default 0 X X 0 0 1 0 0
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HCSB: The HCSB bit enables the internal generation and insertion of the HCS octet into the transmit cell stream. When HCSB is a logic zero, the HCS is generated and inserted internally. When HCSB is a logic one, the HCS octet read from the FIFO is inserted unaltered into the transmit cell stream. An HCS is generated for idle/unassigned cells regardless of the state of this bit. DHCS: The DHCS bit controls the insertion of HCS errors for diagnostic purposes. When DHCS is a logic one, the HCS octet is inverted prior to insertion in the transmit stream. DHCS takes effect unconditionally regardless of whether an idle/unassigned cell is being transmitted or whether the HCS octet has been read from the FIFO. FOVRI: The FOVRI bit is the transmit FIFO overrun interrupt status bit. FOVRI is a logic one when a FIFO overrun occurs. This bit is cleared when this register is read. TSOCI: The TSOCI bit is a logic one when the TSOC input is sampled high during any position other than the first word of the cell data structure. The write address counter is reset to the first word of the data structure when TSOC is sampled high. This bit is cleared when this register is read. FIFOE: The FIFOE bit enables the generation of an interrupt due to a FIFO overrun error condition, or when the TSOC input is sampled high during any position other than the first word of the cell data structure. When FIFOE is a logic one, the interrupt is enabled.
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Register 0x61: TACP Idle/Unassigned Cell Header Pattern Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GFC[3:0]: The GFC[3:0] bits contain the first, second, third, and fourth bit positions of the first octet of the idle/unassigned cell pattern. Cell rate decoupling is accomplished by transmitting idle/unassigned cells when the TACP detects that no outstanding cells exist in the transmit FIFO. The all-zeros pattern is transmitted in the VCI and VPI fields of the idle cell. PTI[2:0]: The PTI[2:0] bits contain the fifth, sixth, and seventh bit positions of the fourth octet of the idle/unassigned cell pattern. Idle cells are transmitted when the TACP detects that no outstanding cells exist in the transmit FIFO. CLP: The CLP bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. Idle cells are transmitted when the TACP detects that no outstanding cells exist in the transmit FIFO. Type R/W R/W R/W R/W R/W R/W R/W R/W Function GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP Default 0 0 0 0 0 0 0 0
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Register 0x62: TACP Idle/Unassigned Cell Payload Octet Pattern Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICP[7:0]: The ICP[7:0] bits contain the pattern inserted in the payload octets of the idle or unassigned cell. Cell rate decoupling is accomplished by transmitting idle/unassigned cells when the TACP detects that no outstanding cells exist in the transmit FIFO. Bit ICP[7] corresponds to the most significant bit of the octet, and the first bit transmitted. Type R/W R/W R/W R/W R/W R/W R/W R/W Function ICP[7] ICP[6] ICP[5] ICP[4] ICP[3] ICP[2] ICP[1] ICP[0] Default 0 1 1 0 1 0 1 0
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Register 0x63: TACP FIFO Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCSCTLEB: The HCSCTLEB bit enables the XORing of the HCS Control byte with the generated HCS before insertion into the transmit stream. When HCSCTLEB is a logic zero, the HCS Control byte provided in the third word of the 27 word data structure is XORed with the generated HCS. When HCSCTLEB is a logic one, the HCS Control byte is ignored. TCALEVEL0: The TCALEVEL0 bit controls the function of the TCA output. When TCALEVEL0 is a logic one, a high to low transition on output TCA indicates that the transmit FIFO is full. When TCALEVEL0 is a logic zero, a high to low transition on output TCA indicates that the transmit FIFO is almost full and can accept no more than four additional writes. Refer to the Drop Side Transmit Interface timing diagram in the Functional Timing section. FIFODP[1:0]: The FIFODP[1:0] bits determine the transmit FIFO cell depth. FIFO depth control is important in systems where the cell latency through the transmit FIFO must be minimized. When the FIFO is filled to the specified depth, the transmit cell available signal, TCA transitions to logic zero. The selectable FIFO cell depths are shown below: Type R/W R/W R R R/W R/W R/W R/W Function TXPTYPE TXPRTYE TXPRTYI[1] TXPRTYI[0] FIFODP[1] FIFODP[0] TCALEVEL0 HCSCTLEB Default 0 0 X X 0 0 0 1
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FIFODP[1] 0 0 1 1 TXPRTYI[1:0]:
FIFODP[0] 0 1 0 1
FIFO DEPTH 4 cells 3 cells 2 cells 1 cell
The TXPRTYI[1:0] bits indicate if a parity error was detected on the TDAT[15:0] bus. When TXPRTYI[1] is a logic one, a parity error has been detected over inputs, TDAT[15:8]. Similarly, when TXPRTYI[0] is a logic one, a parity error has been detected over inputs, TDAT[7:0]. Both bits are cleared when this register is read. Odd or even parity is selected using the TXPTYPE bit. TXPRTYE: The TXPRTYE bit enables transmit parity interrupts. When TXPRTYE is a logic one, parity errors on inputs TDAT[15:0] generate an interrupt. TXPTYPE: The TXPTYPE bit selects even or odd parity for inputs TXPRTY[1:0]. When TXPTYPE is a logic one, input TXPRTY[1] is the even parity bit for inputs TDAT[15:8] while input TXPRTY[0] is the even parity bit for inputs TDAT[7:0]. When TXPTYPE is a logic zero, inputs TXPRTY[1:0] are the odd parity bits for inputs TDAT[15:0].
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Register 0x64: TACP Transmit Cell Counter (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[7] TCELL[6] TCELL[5] TCELL[4] TCELL[3] TCELL[2] TCELL[1] TCELL[0] Default X X X X X X X X
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Register 0x65: TACP Transmit Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[15] TCELL[14] TCELL[13] TCELL[12] TCELL[11] TCELL[10] TCELL[9] TCELL[8] Default X X X X X X X X
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Register 0x66: TACP Transmit Cell Counter (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCELL[20:0]: The TCELL[20:0] bits indicate the number of cells read from the transmit FIFO and inserted into the transmit stream during the last accumulation interval. Idle/Unassigned cells inserted in the transmit stream are not counted. The counter should be polled every second to avoid saturation. The contents of these registers are valid 2s after a transfer is triggered by a write to the transmit cell count register space. The count can also be polled by writing to the S/UNI-PLUS Master Reset and Identity / Load Performance Meters register (0x00). Writing to register address 0x00 loads all the counter registers in the RSOP RLOP RPOP , , , RACP and TACP blocks. R R R R R Type Function Unused Unused Unused TCELL[20] TCELL[19] TCELL[18] TCELL[17] TCELL[16] Default X X X X X X X X
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Register 0x67: TACP Fixed Stuff / GFC Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function TGFCE[3] TGFCE[2] TGFCE[1] TGFCE[0] FSEN TXBYTEPRTY FIXBYTE[1] FIXBYTE[0] Default 0 0 0 0 1 0 0 0
FIXBYTE[1:0]: The FIXBYTE[1:0] bits identify the byte pattern inserted into fixed byte columns of the synchronous payload envelope. FIXBYTE[1] 0 0 1 1 TXBYTEPRTY: The transmit byte parity, TXBYTEPRTY, bit selects between byte parity and word parity mode for inputs TXPRTY[1:0]. When the TXBYTEPRTY bit is set to logic one, byte parity mode is selected; otherwise, word parity mode is selected. In byte parity mode, TXPRTY[1] is the parity bit for inputs TDAT[15:8], and TXPRTY[0] is the parity bit for inputs TDAT[7:0]. In word parity mode, TXPRTY[1] is the parity bit for inputs TDAT[15:0], and TXPRTY[0] is unused. Word parity mode can only be selected when the BUS8 input is low (i.e., the 16-bit FIFO interface is selected). FIXBYTE[0] 0 1 0 1 BYTE 00H 55H AAH FFH
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FSEN: The FSEN bit determines the payload mapping of ATM cells when STS-1 (AU-3) mapping is selected. When FSEN is a logic one, the S/UNI-PLUS does not map ATM cells into columns 30 and 59 of the STS-1 SPE. When FSEN is a logic zero, the S/UNI-PLUS maps ATM cells into the entire STS-1 SPE. The FSEN bit is ignored in STS-3c (STM-1) modes. TGFCE[3:0]: The TGFCE[3:0] bits select the source of the GFC bits. When a TGFCE[3:0] bit is a logic one, the TGFC input is used to source the corresponding GFC[3:0] bit of transmit cell headers. If a TGFCE[3:0] bit is a logic zero, the corresponding GFC[3:0] bit of an idle/unassigned cell (as programmed in the TACP Idle/Unassigned Cell Header register) or the corresponding GFC[3:0] bit of a cell read from the FIFO is transmitted unaltered.
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Register 0x68: SPTB Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W R/W Type Function Unused RRAMACC RTIUIE RTIMIE PER5 TNULL NOSYNC LEN16 Default X 0 0 0 0 1 0 0
This register controls the receive and transmit portions of the SPTB. LEN16: The LEN16 bit selects the length of the path trace message to be 16 bytes or 64 bytes. When LEN16 is a logic one, a 16 byte path trace message is selected. When LEN16 is a logic zero, a 64 byte path trace message is selected. NOSYNC: The NOSYNC bit disables the writing of the path trace message into the trace buffer to be synchronized to the content of the message. When LEN16 is a logic one and NOSYNC is a logic zero, the receive path trace message byte with its most significant bit set will be written to the first location in the buffer. When LEN16 and NOSYNC are logic zero, the byte after the carriage return/linefeed (CR/LF) sequence will be written to the first location in the buffer. When NOSYNC is a logic one, synchronization is disabled, and the path trace message buffer behaves as a circular buffer. TNULL: The TNULL bit controls the insertion of an all-zero path trace identifier message in the transmit stream. When TNULL is a logic one, the contents of the transmit buffer is ignored and all-zeros bytes are inserted. When TNULL is a logic zero, the contents of the transmit path trace buffer are inserted into
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the J1 byte. TNULL should be set high before changing the contents of the trace buffer to avoid sending partial messages. PER5: The PER5 bit controls the number of times a path trace identifier message must be received unchanged before being accepted. When PER5 is a logic one, a message is accepted when it is received unchanged five times consecutively. When PER5 is a logic zero, the message is accepted after three identical repetitions. RTIMIE: The RTIMIE bit controls the activation of the interrupt output when the comparison between accepted identifier message and the expected message changes state. When RTIMIE is a logic one, changes in match state activates the interrupt (INTB) output. RTIUIE: The RTIUIE bit controls the activation of the interrupt output when the receive identifier message changes state. When RTIUIE is a logic one, changes in the received path trace identifier message stable/unstable state activates the interrupt output. RRAMACC: The RRAMACC bit directs read and writes access to either the receive or transmit path trace buffer. When RRAMACC is a logic one, microprocessor accesses are directed to the receive path trace buffer. When RRAMACC is a logic zero, microprocessor accesses are directed to the transmit path trace buffer.
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Register 0x69: SPTB Path Trace Identifier Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R Function BUSY Unused Unused Unused RPTIUI RPTIUV RPTIMI RPTIMV Default 0 X X X X X X X
This register reports the path trace identifier status of the SPTB. RPTIMV: The RPTIMV bit reports the match/mismatch status of the identifier message framer. RPTIMV is a logic one when the accepted identifier message differs from the expected message written by the microprocessor. RPTIMV is a logic zero when the accepted message matches the expected message. RPTIMI: The RPTIMI bit is a logic one when match/mismatch status of the trace identifier framer changes state. This bit is cleared when this register is read. RPTIUV: The RPTIUV bit reports the stable/unstable status of the identifier message framer. RPTIUV is a logic one when the current received path trace identifier message has not matched the previous message for eight consecutive messages. RPTIUV is a logic zero when the current message becomes the accepted message as determined by the PER5 bit in the SPTB Control register. RPTIUI: The RPTIUI bit is a logic one when the stable/unstable status of the trace identifier framer changes state. This bit is cleared when this register is read.
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BUSY: The BUSY bit reports whether a previously initiated indirect read or write to a message buffer has been completed. BUSY is set to a logic one immediately upon writing to the SPTB Indirect Address register and stays high until the initiated access is completed (about 0.6 s in STS-3 or 1.8 s in STS-1). This register should be polled to determine when new data is available in the SPTB Indirect Data register.
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Register 0x6A: SPTB Indirect Address Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0] Default 0 0 0 0 0 0 0 0
This register supplies the address used to index into path trace identifier buffers. A[6:0]: The indirect read address bits (A[6:0]) are used to address the path trace identifier buffers. When RRAMACC is set high, addresses 0 to 63 reference the captured message page while addresses 64 to 127 reference the expected message page of the receive path trace buffer. The captured message page contains the identifier bytes extracted from the receive stream. The expected message page contains the path trace message to which the captured message page is compared. When RRAMACC is set low, addresses 0 to 63 reference the transmit path trace buffer which contains the path trace message inserted in the transmit stream. RWB: The access control bit (RWB) selects between an indirect read or write access to the selected path trace buffer (receive or transmit as determined by the RRAMACC bit). Writing to this register initiates an access to the selected path trace buffer. When RWB is a logic one, a read access is initiated. The addressed location's contents are placed in the SPTB Indirect Data register. When RWB is a logic zero, a write access is initiated. The data in the SPTB Indirect Data register is written to the addressed location in the selected buffer.
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Register 0x6B: SPTB Indirect Data Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default 0 0 0 0 0 0 0 0
This register contains the data read from the path trace message buffer after a read operation or the data to be written into the buffer during a write operation. D[7:0]: The indirect data bits (D[7:0]) contains the data read from either the transmit or receive path trace buffer after an indirect read operation is completed. The data that is written to a buffer is set up in this register before initiating the indirect write operation.
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Register 0x6C: SPTB Expected Path Signal Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function EPSL7 EPSL6 EPSL5 EPSL4 EPSL3 EPSL2 EPSL1 EPSL0 Default 0 0 0 0 0 0 0 0
This register contains the expected path signal label byte in the receive stream. EPSL[7:0]: The EPSL[7:0] bits contain the expected path signal label byte (C2). EPSL[7:0] is compared with the accepted path signal label extracted from the receive stream. A path signal label match or mismatch is declared based upon the following table:
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Table 3 Expect 00 00 00 01 01 01 XX XX XX XX
Receive 00 01 XX 00 01 XX 00 01 XX YY Action Match Mismatch Mismatch Mismatch Match Match Mismatch Match Match Mismatch
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Register 0x6D: SPTB Path Signal Label Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R/W R/W Function RPSLUIE RPSLMIE Unused Unused RPSLUI RPSLUV RPSLMI RPSLMV Default 0 0 X X X X X X
This register reports the path signal label status of the SPTB. RPSLMV: The RPSLMV bit reports the match/mismatch status between the expected and the accepted path signal label. RPSLMV is a logic one when the accepted PSL results in a mismatch with the expected PSL written by the microprocessor. RPSLMV is a logic zero when the accepted PSL results in a match with the expected PSL. RPSLMI: The RPSLMI bit is a logic one when the match/mismatch status between the accepted and the expected path signal label changes state. This bit is cleared when this register is read. RPSLUV: The RPSLUV reports the stable/unstable status of the path signal label in the receive stream. RPSLUV is a logic one when the current received C2 byte differs from the previous C2 byte for five consecutive frames. RPSLUV is a logic zero when the same PSL code is received for five consecutive frames. RPSLUI: The RPSLUI bit is a logic one when the stable/unstable status of the path signal label changes state. This bit is cleared when this register is read.
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RPSLMIE: The RPSLMIE bit is the interrupt enable for the path signal label match/mismatch status. When RPSLMIE is a logic one changes in the match state generate an interrupt. RPSLUIE: The RPSLUIE bit is the interrupt enable for the path signal label stable/unstable status. When RPSLUIE is a logic one, changes in the stable/unstable state generate an interrupt.
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Register 0x70: BERM Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W Type R/W Function BERTEN Unused Unused Unused Unused Unused Unused BERE Default 0 X X X X X X 0
This register controls the automatic bit error rate alarm circuitry. BERE: The BERE bit is the interrupt enable for bit error rate threshold events. When BERE is a logic one, an interrupt is generated when the bit error rate threshold is exceeded. BERTEN: The BERTEN bit enables and disables automatic monitoring of line bit error rate threshold events. When BERTEN is a logic one, the S/UNI-PLUS continuously accumulates line BIP errors over a period defined in the BERM Line BIP Accumulation Period registers. If at any point the accumulated count exceeds the value defined in the BERM Line BIP Threshold registers, a bit error rate threshold event is generated. Both the BERM Line BIP Accumulation Period and BERM Line BIP Threshold registers should be set up before the monitoring is enabled. When BERTEN is a logic zero, the BIP accumulation logic is disabled.
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Register 0x71: BERM Interrupt Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Type Function Unused Unused Unused Unused Unused Unused Unused BERI Default X X X X X X X X
This register indicates the bit error rate threshold events. BERI: The BERI bit indicates that the incoming bit error rate has exceeded the user programmed threshold. When BERI is a logic one, incoming B2 errors have exceeded the programmable threshold. This bit is cleared when this register is read.
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Register 0x72: BERM Line BIP Accumulation Period LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function LB_AP[7] LB_AP[6] LB_AP[5] LB_AP[4] LB_AP[3] LB_AP[2] LB_AP[1] LB_AP[0] Default 0 0 0 0 0 0 0 0
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Register 0x73: BERM Line BIP Accumulation Period MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LB_AP[15:0]: The LB_AP[15:0] bits represent the number of 125 s frames that define a line BIP accumulation period. Refer to the Operations section for the recommended settings. Type R/W R/W R/W R/W R/W R/W R/W R/W Function LB_AP[15] LB_AP[14] LB_AP[13] LB_AP[12] LB_AP[11] LB_AP[10] LB_AP[9] LB_AP[8] Default 0 0 0 0 0 0 0 0
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Register 0x74: BERM Line BIP Threshold LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function LB_TH[7] LB_TH[6] LB_TH[5] LB_TH[4] LB_TH[3] LB_TH[2] LB_TH[1] LB_TH[0] Default 0 0 0 0 0 0 0 0
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Register 0x75: BERM Line BIP Threshold MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LB_TH[15:0]: The LB_TH[15:0] bits represent the allowable number of line BIP errors that can be accumulated during a line BIP accumulation period before an BER threshold event is asserted. Refer to the Operations section for the recommended settings. Type R/W R/W R/W R/W R/W R/W R/W R/W Function LB_TH[15] LB_TH[14] LB_TH[13] LB_TH[12] LB_TH[11] LB_TH[10] LB_TH[9] LB_TH[8] Default 0 0 0 0 0 0 0 0
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11
TEST FEATURES DESCRIPTION Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the S/UNI-PLUS. Test mode registers (as opposed to normal mode registers) are selected when TRS (A[7]) is high. Test mode registers may also be used for board testing. When all of the TSBs within the S/UNI-PLUS are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "Test Mode 0" for details). In addition, the S/UNI-PLUS also supports a standard IEEE 1149.1 five signal JTAG boundary scan test port for use in board testing. All digital device inputs may be read and all digital device outputs may be forced via the JTAG test port with the exception of the PECL pins and the analog pins.
11.1
Test Mode Register Memory Map Address 0x00-0x7F 0x80 0x81 0x82-0x84 0x85 0x86 0x87-0x8B 0x8C 0x8D-0x8F 0x90 0x91 0x92 Register Normal Mode Registers Master Test Analog Test Register 0 Reserved CSU Test Register 0 CRU Test Register 0 Reserved TTOP Test Register 0 Reserved RSOP Test Register 0 RSOP Test Register 1 RSOP Test Register 2
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Address 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B-0x9F 0xA0 0xA1 0xA2 0xA3 0xA4-0xA7 0xA8 0xA9 0xAA 0xAB 0xAC-0xAF 0xB0 0xB1 0xB2 0xB3-0xBF 0xC0 0xC1 0xC2 0xC3
Register RSOP Test Register 3 TSOP Test Register 0 TSOP Test Register 1 TSOP Test Register 2 TSOP Test Register 3 RLOP Test Register 0 RLOP Test Register 1 RLOP Test Register 2 Reserved TLOP Test Register 0 TLOP Test Register 1 TLOP Test Register 2 TLOP Test Register 3 Reserved SSTB Test Register 0 SSTB Test Register 1 SSTB Test Register 2 SSTB Test Register 3 Reserved RPOP Test Register 0 RPOP Test Register 1 RPOP Test Register 2 Reserved TPOP Test Register 0 TPOP Test Register 1 TPOP Test Register 2 TPOP Test Register 3
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Address 0xC4 0xC5-0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5-0xDF 0xE0 0xE1 0xE2 0xE3 0xE4-0xE7 0xE8 0xE9 0xEA 0xEB 0xEC-0xEF 0xF0 0xF1 0xF2-0xFF
Register TPOP Test Register 4 Reserved RACP Test Register 0 RACP Test Register 1 RACP Test Register 2 RACP Test Register 3 RACP Test Register 4 Reserved TACP Test Register 0 TACP Test Register 1 TACP Test Register 2 TACP Test Register 3 Reserved SPTB Test Register 0 SPTB Test Register 1 SPTB Test Register 2 SPTB Test Register 3 Reserved BERM Test Register 0 BERM Test Register 1 Reserved
Notes on Test Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read.
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2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
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Register 0x80: Master Test Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W W W R/W W R/W Type R/W Function TT_BYP Unused PMCATST PMCTST DBCTRL IOTST HIZDATA HIZIO Default 0 X X X X 0 X 0
This register is used to enable S/UNI-PLUS test features. All bits, except PMCTST and PMCATST, are reset to zero by a reset of the S/UNI-PLUS. HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-PLUS . While the HIZIO bit is a logic one, all output pins of the S/UNI-PLUS except the data bus and output TDO are held tri-state. The microprocessor interface is still active. While the HIZDATA bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. The HIZDATA bit is overridden by the DBCTRL bit. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each TSB block in the S/UNI-PLUS for board level testing. When IOTST is a logic one, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequentially the device outputs (refer to the "Test Mode 0 Details" in the "Test Features" section). DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic one and either IOTST or PMCTST are logic one, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the S/UNI-PLUS to
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drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. PMCTST: The PMCTST bit is used to configure the digital portion of the S/UNI-PLUS for PMC's manufacturing tests. When PMCTST is set to logic one, the S/UNI-PLUS microprocessor port becomes the test access port used to run the PMC manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can be cleared by setting CSB to logic one or by writing logic zero to the bit. PMCATST: The PMCATST bit is used to configure the analog portion of the S/UNI-PLUS for PMC's manufacturing tests. When PMCATST is set to logic one, the S/UNI-PLUS microprocessor port becomes the test access port used to run the PMC manufacturing analog test vectors. The PMCATST bit is logically "ORed" with the IOTST bit, and can be cleared by setting CSB to logic one or by writing logic zero to the bit. TT_BYP: The TT_BYP bit is used to bypass the glue logic on the TTOH and TTOHEN input pins to permit direct access to the TTOP block. When TT_BYP is set to logic one, the glue logic is bypassed, and TTOH and TTOHEN feed directly into the TTOP block. When TT_BYP is set to logic zero, the glue logic is not bypassed, and TTOH and TTOHEN pass through the glue logic before entering the TTOP block. 11.2 Test Mode 0 Details In test mode 0, the S/UNI-PLUS allows the logic levels on the device inputs to be read through the microprocessor interface, and allows the device outputs to be forced to either logic level through the microprocessor interface. The IOTST bit in the Master Test register should be set to logic one. To enable test mode 0, the IOTST bit in the Master Test register is set to logic one and the following addresses must be written with 00H: 91H, 95H, 99H, A1H, A5H, A7H, A9H, B1H, C1H, D1H, E1H, E9H, F1H. Clock edges must be provided on inputs TFCLK and RFCLK.
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Reading the following address locations returns the values on the indicated inputs: Table 5
Addr 07H 0FH 94H A0H C0H C3H C4H D0H E0H XOFF BUS8 TGFC TSUC1 TSOW1 TLOW TSD TLD TLDRI2 TPRDI3 TPAIS TPOH4 TPOHEN5 TFP TLAIS TCLK Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 PIP[3] Bit 2 PIP[2] Bit 1 PIP[1] TTOH Bit 0 PIP[0] TTOHEN
The following inputs cannot be read using the IOTST feature: TDAT[15:0], TSOC, TXPRTY[1:0], TWRENB, TFCLK, RFCLK, TSEN, RRDENB, D[7:0], A[7:0], ALE, CSB, WRB, RDB, RSTB, TRSTB, TMS, TCK, and TDI. 1. TOWCLK must be toggled to a logic zero and then back to a logic one in order to capture the value on these inputs. 2. To read TLDRI, AUTOLRDI must be set to 0 in the Master Auto Alarm/Monitor Register. 3. To read TPRDI, AUTOPRDI must be set to 0 in the Master Auto Alarm/Monitor Register. 4. To read TPOH, TPOHEN must be set to a logic one. 5. To read TPOHEN, TPTBEN must be set to 0 in the Master Configuration Register. Writing the following address locations forces the outputs to the value in the corresponding bit position (zeros should be written to all unused test register locations):
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Table 6
Addr 07H 90H 92H 94H 96H 98H 9AH 9BH A0H B0H B2H B3H C2H C3H D0H E0H Bit 7
Bit 6 POP[2] Bit 5 POP[1] LOF RSOW Bit 4 POP[0] OOF LOS RSD TSDCLK TOHFP LRDI LAIS RLD ROHFP3 RLDCLK RTOHFP3 TOWCLK PAIS LOP PRDI RPOHFP RPOH TTOHCLK TPOHCLK RCP RGFC TPOHFP LCD TCP INT1 RPOHCLK TTOHFP TLDCLK RLOW RTOHCLK3 ROWCLK RTOH3 RSDCLK RSUC Bit 3 Bit 2 Bit 1 Bit 0
POP[3]
The following outputs can not be controlled using the IOTST feature: TCA, RSOC, RDAT[15:0], RXPRTY[1:0], RCA, D[7:0], and TDO. 1. INT corresponds to output INTB. INTB is an open drain output and should be pulled high for proper operation. Writing a logic one to the INT bit allows the S/UNI-PLUS to drive INTB low. Writing a logic zero to the INT bit tristates the INTB output. 2. To control these outputs, RMODE[1:0] should be set to binary '10' in the Master Configuration Register. 3. To control GTOCLK, TMODE[1:0] should be set to binary '11' in the Master Configuration Register. 11.3 JTAG Test Port The S/UNI-PLUS JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and
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boundary scan. Using the TAP device input logic levels can be read, device , outputs can be forced, the device can be identified and the device boundary scan path can be bypassed. For more details on the JTAG port, please refer to the Operation section.
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12
OPERATION This section presents PCB design recommendations, tutorial information on the SONET/SDH transmission convergence sublayer for ATM, the SCI-PHYTM compliant cell data structures, and operating details for the JTAG boundary scan feature.
12.1
Board Design Recommendations The noise environment and signal integrity are often the limiting factors in system performance. Therefore, the following board design guidelines must be followed in order to ensure proper operation. 1. Connect digital and analog grounds together at a point where the ground reference is clean and as free as possible of digital return currents. Typically, this means as close as possible to the PCB connector where ground is brought into the card. 2. Provide separate +5 volt analog transmit, +5 volt analog receive, and +5 volt digital supplies, but otherwise connect the supply voltages together at a point where the supply is clean and as free as possible of digitally induced switching noise. Typically, this means as close as possible to the PCB connector where +5 volts is brought into the card. In some systems separate regulation is required for the transmit and receive analog supplies. 3. Ferrite beads are not advisable in digital switching circuits because inductive spiking (di/dt noise) is introduced into the power rail. Simple RC filtering is probably the best approach provided care is taken to ensure the IR drop in the resistor does not lower the supply voltage below the recommended operating voltage. 4. Ferrite beads are recommended for TAVD1, TAVD2, RAVD1 and RAVD2. 5. Separate high-frequency decoupling capacitors are recommended for each analog power (TAVD1, TAVD2, RAVD1 and RAVD2) pin as close to the package pin as possible. Separate decoupling is required to prevent the transmitter from coupling noise into the receiver and to prevent transients from coupling into the reference circuitry powered by TAVD1 and RAVD1. 6. The high speed serial streams (TXD+/- and RXD+/) must be routed with controlled impedance circuit board traces and must be terminated with a
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matched load. Normal TTL-type design rules are not recommended and will reduce the performance of the device. 12.2 Interfacing to ECL or PECL Devices Although the TXD+/- outputs are TTL compatible, only a few passive components are required to convert the signals to ECL (or PECL) logic levels. Figure 10 illustrates the recommended configuration. The capacitors AC couple the outputs so that the ECL inputs are free to swing around the ECL bias voltage (VBB). The combination of the 237 and 50 resistors divide the voltage down to a nominally 800mV swing. The 50 resistors also terminate the signals. Similarly, the RXD+/- inputs to the S/UNI-PLUS are AC coupled as shown in Figure 10. The S/UNI-PLUS inputs are self-biasing to improve operating speed and waveform symmetry. For this reason, the DC blocking capacitors are always required, even when interfacing to PECL drivers. The only exception are the ALOS+/- inputs which must be DC coupled because of their low frequency content. Ceramic coupling capacitors are recommended. Figure 10 - Interfacing S/UNI-PLUS to ECL or PECL
ECL or PECL Driving S/UNI-PLUS
S/UNI-PLUS Driving ECL or PECL 10nF TXD+ S/UNI-PLUS TXD50 50 10nF 237 Zo=50 237 Zo=50
+
ECL BUFFER
+
ECL BUFFER 330
Zo=50
10nF RXD+
100 Zo=50 10nF
S/UNI-PLUS RXD-
-
-
330
VBB
V EE
12.3
Driving Differential Inputs Single Ended In some applications it may be more cost effective or technically desirable to drive the RRCLK+/-, TRCLK+/- or ALOS+/- inputs with a single ended PECL, TTL or CMOS signal. Figure 11 illustrates the suggested configuration to achieve this.
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Note that the RXD+/- inputs do not support single ended operation and must always be driven by a differential source. Figure 11 - Single Ended Driving Differential Inputs
+
TTL or CMOS signal S/UNI-PLUS PECL INPUTS
0.01F
+
S/UNI-PLUS PECL INPUTS
-
PECL signal
-
For TTL or CMOS signals, the positive input must be grounded. The negative input should be connected directly to a TTL or CMOS signal. In the case where a single ended PECL source is to be used, the positive input should be decoupled to ground through a 0.01F capacitor. These configurations logically invert the input signal. 12.4 Clock Recovery Figure 12 is an abstraction of the clock recovery phase lock loop illustrating the connections to external components. The figure illustrates the unity gain buffer loop filter application where the integral op-amp output is buffered through a unity gain amplifier to minimize the effect of its finite output impedance on the transfer function of the PLL. The unity gain buffer loop filter circuit typically exceeds SONET/SDH jitter tolerance and jitter transfer specifications and is recommended for all designs.
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Figure 12
-
RAVD2
RXD+/RRCLK+/-
Phase/Freq Detector
Prefilter
OpAmp
VCO
recovered clock
on-chip off-chip
RAVS2
LF+
LFRAVD2
LFO
R2 C2
R1 C1
2N3904
RE
Table 7 Line Rate (Mbit/s) 155.52 51.84
R1 (1%) 68.1 68.1 R2 (1%) 90.9 90.9 C1, C2 min (F) 4.7 15 RE (1%) 100 100
The capacitors (C1, C2) determine the amount of "peaking" in the jitter transfer curve. The capacitor values can be 10%. The capacitors should be nonpolarized because when the S/UNI-PLUS is held in reset, the capacitors are reverse-biased at approximately 2.0V. Also, for some process extremes, the capacitors may operate with a D.C. reverse-bias of up to 1.0V. 12.5 ATM Mapping and Overhead Byte Usage The S/UNI-PLUS processes the ATM cell mappings for STS-3c (STM-1) and STS-1 as shown below in figures 12 and 13. The S/UNI-PLUS processes the transport and path overhead required to support ATM UNIs and NNIs. In addition, the S/UNI-PLUS provides support for the APS bytes, the data
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communication channels and provides full external control and observability of the transport and path overhead bytes. In Figure 13, the STS-1 mapping is displayed. The S/UNI-PLUS supports two STS-1 mappings, one with the indicated stuff columns containing fixed stuff bytes and the other with the indicated stuff columns used for ATM cells. Figure 13 - STS-1 Mapping
90 bytes 3 bytes STS-1 Transport Overhead
A1 A2 J0 Section Overhead Pointer B1 E1 F1 D1 D2 D3 H1 H2 H3 B2 K1 K2 Line Overhead D4 D5 D6 H4 D7 D8 D9 Z3 D10 D11 D12 Z4 S1 M0 E2 Z5 C2 G1 F2 J1 B3
87 bytes
Column 1
Column 30 ATM Cell
Column 59
F I X E D ATM Cell S T U F F
F I X E D S T U F F ATM Cell
9 bytes
* Fixed stuff columns optionally filled with cells
In Figure 14, the STS-3c (STM-1) mapping is shown. In this mapping, no stuff columns are included in the SPE. The entire SPE is used for ATM cells.
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Figure 14
- STS-3c (STM-1) Mapping
270 bytes
9 bytes
Section Overhead (Regen. Section) Pointer J1 B3 C2 G1 Line Overhead (Multiplex Section) F2 H4 Z3 Z4 Z5
261 bytes
ATM Cell
ATM Cell
9 bytes
ATM Cell
ATM Cell
STS-3c Transport Overhead STM-1 Section Overhead
A1 A1 A1 A2 A2 A2 J0 Z0 Z0 B1 D1 E1 D2 F1 D3
H1 H1 H1 H2 H2 H2 H3 H3 H3 B2 B2 B2 K1 D4 D7 D10 D5 D8 D11 K2 D6 D9 D12
S1 Z1 Z1 Z2 Z2 M1 E2
Transport Overhead Bytes A1, A2: J0 The frame alignment bytes (A1, A2) locate the SONET frame in the STS-3c/1 (STM-1) serial stream. The J0 byte is currently defined as the STS-1/STM-1 section trace byte for SONET/SDH. J0 byte is not scrambled by the frame synchronous scrambler. The Z0 bytes are currently defined as the STM-1 section growth bytes for SONET/SDH. Z0 bytes are not scrambled by the frame synchronous scrambler.
Z0:
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B1: E1:
The section bit interleaved parity byte provides a section error monitoring function. The section orderwire byte provides a 64 kbit/s craftperson voice channel for network element to network element communication. The section user channel byte provides a 64 kbit/s data channel for use by the network provider. The section data communications channel provides a 192 kbit/s data communications channel for network element to network element communications. The pointer value bytes locate the path overhead column in the SONET/SDH frame. The pointer action bytes contain synchronous payload envelope data when a negative stuff event occurs. The all zeros pattern is inserted in the transmit direction. This byte is ignored in the receive direction unless a negative stuff event is detected. The line bit interleaved parity bytes provide a line error monitoring function. The K1 and K2 bytes provide the automatic protection switching channel. The K2 byte is also used to identify line layer maintenance signals. Line RDI is indicated when bits 6, 7, and 8 of the K2 byte are set to the pattern '110'. Line AIS is indicated when bits 6, 7, and 8 of the K2 byte are set to the pattern '111'. The line data communications channel provides a 576 kbit/s data communications channel for network element to network element communications. The S1 byte provides the synchronization status byte. Bits 5 through 8 of the synchronization status byte identifies the synchronization source of the STS-3c/1 (STM-1) signal. Bits 1 through 4 are currently undefined.
F1: D1 - D3:
H1, H2: H3:
B2: K1, K2:
D4 - D12:
S1:
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Z1: M0:
The Z1 bytes are located in the second and third STS-1s of a STS-3c (STM-1) and are allocated for future growth. The M0 byte is defined only for STS-1, and bits 5 through 8 provide a line far end block error function for remote performance monitoring. Bits 1 through 4 are currently undefined. The M1 byte is located in the third STS-1 of a STS-3c (STM1) and provides a line far end block error function for remote performance monitoring. The Z2 bytes are located in the first and second STS-1s of a STS-3c (STM-1) and are allocated for future growth. The line orderwire byte provides a 64 kbit/s craftperson voice channel for network element to network element communication.
M1:
Z2: E2:
Path Overhead Bytes J1: The Path Trace byte is used to repetitively transmit a 64-byte CLLI message (for SONET networks), or a 16-byte E.164 address (for SDH networks). When not used, this byte should be set to transmit continuous null characters. Null is defined as the ASCII code, 0x00. The path bit interleaved parity byte provides a path error monitoring function. The path signal label indicator identifies the equipped payload type. For ATM payloads, the identification code is 0x13. The path status byte provides a path FEBE function, and a path remote defect indication function. Two bits are allocated for remote defect indications: bit 5 (the path RDI bit) and bit 6 (the auxiliary path RDI bit). Taken together these bits provide a four state path RDI code that can be used to categorize path defect indications. The path user channel byte provides a 64 kbit/s data channel for use by the network provider.
B3: C2:
G1:
F2:
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H4:
The multiframe indicator byte is a payload specific byte, and is not used for ATM payloads. This byte is forced to 0x00 in the transmit direction, and is ignored in the receive direction. The path growth bytes provide three unused bytes for future use.
Z3 - Z5: 12.6
Cell Data Structure ATM cells may be passed to/from the S/UNI-PLUS using a twenty-seven word data structure or a fifty-three word data structure. These data structures are shown in Figure 15 and Figure 16. Figure 15 - 16-bit Wide, 27 Word Structure Bit 15 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 H1 H3 H5 PAYLOAD1 PAYLOAD3 PAYLOAD5 Bit 8 Bit 7 H2 H4
HCS STATUS/CONTROL
Bit 0
PAYLOAD2 PAYLOAD4 PAYLOAD6
Word 27
PAYLOAD47
PAYLOAD48
The 16-bit SCI-PHY compliant data structure is selected when the BUS8 input is tied low. Bit 15 of each word is the most significant bit (which corresponds to the first bit transmitted or received). The header check sequence octet (HCS) is passed through this structure. The start of cell indication input and output (TSOC
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and RSOC) are coincident with Word 1 (containing the first two header octets). Word 3 of this structure contains the HCS octet in bits 15 to 8. In the receive direction, the lower 8 bits of Word 3 contain the HCS status octet. An all-zeros pattern in these 8 bits indicates that the associated header is error free. An all-ones pattern indicates that the header contains an uncorrectable error (if the HCSPASS bit in the RACP Control Register is set to logic zero, the all-ones pattern will never be passed in this structure). An alternating ones and zeros pattern (0xAA) indicates that the header contained a correctable error. In this case the header passed through the structure is the "corrected" header. In the transmit direction, the HCS bit in the TACP Control register determines whether the HCS is calculated internally or is inserted directly from the upper 8 bits of Word 3. The lower 8 bits of Word 3 contain the HCS control octet. The HCS control octet is an error mask that allows the insertion of one or more errors in the HCS octet. A logic one in a given bit position causes the inversion of the corresponding HCS bit position (for example a logic one in bit 7 causes the most significant bit of the HCS to be inverted). Figure 16 - 8-bit Wide, 53 Word Structure Bit 7 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 H1 H2 H3 H4 H5 PAYLOAD1 Bit 0
Word 53
PAYLOAD48
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The 8-bit SCI-PHY compliant data structure is selected when the BUS8 input is tied high. Bit 7 of each word is the most significant bit (which corresponds to the first bit transmitted or received). The header check sequence octet (HCS) is passed through this structure. The start of cell indication input and output (TSOC and RSOC) are coincident with Word 1 (containing the first cell header octet). Word 5 of this structure contains the HCS octet. In the receive direction, cells containing "detected and uncorrected" header errors are dropped when the HCSPASS bit in the RACP Control/Status Register is set to logic zero. No HCS status information is passed within this data structure. Error free headers and "detected and corrected" headers are passed when HCSPASS is a logic zero. Error free headers, "detected and corrected" headers, and "detected and uncorrected" headers are passed when HCSPASS is a logic one. In the transmit direction, the HCS bit in the TACP Control Register determines whether the HCS is calculated internally or is inserted directly from Word 5. 12.7 Bit Error Rate Monitor The S/UNI-PLUS Bit Error Rate Monitor (BERM) block counts line BIP errors over programmable periods of time and monitors whether the accumulated count of line BIP errors exceeds a programmable threshold within that specific period. The BERM block can be used to trigger an interrupt when the bit error rate (BER) of the line is 50% of the programmed rate. The following tables list the recommended contents of the BERM Line BIP Accumulation Period and BERM Line BIP Threshold Period registers to detect various BERs. In STS-1 mode, the following register contents are recommended: Table 8 BER 10-4 10-5 10-6 Accumulation Period LSB 0x87 0x19 0xFA Accumulation Period MSB 0x01 0x0F 0x9C Threshold LSB 0xCA 0xD9 0xDB Threshold MSB 0x00 0x00 0x00
In STS-3c mode, the following register contents are recommended:
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Table 9 BER 10-4 10-5 10-6 12.8
Accumulation Period LSB 0x85 0x08 0x53 Accumulation Threshold Period MSB LSB 0x00 0x05 0x34 0xCA 0xD9 0xDB Threshold MSB 0x00 0x00 0x00
JTAG Support The S/UNI-PLUS supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO, used to control the TAP controller and the boundary scan registers. The TRSTB input is the active low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown in Figure 17.
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Figure 17
- Boundary Scan Architecture
TDI
Boundary Scan Register Device Identification Register Bypass Register
Instruction Register and Decode
Mux DFF
TDO
TMS
Test Access Port Controller
Control Select Tri-state Enable
TRSTB TCK
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a single bit delay from primary input, TDI to primary output , TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device
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inputs and outputs. Using the boundary scan register, all digital inputs can be sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs. TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described in Figure 18.
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Figure 18
- TAP Controller Finite State Machine
TRSTB=0 Test-Logic-Reset 1 0 1 Run-Test-Idle 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 0 1 Exit1-IR 0 Pause-IR 1 0 Select-DR-Scan 0 1 Capture-IR 0 Shift-IR 1 0 1 1 Select-IR-Scan 0 1
All transitions dependent on input TMS
Test-Logic-Reset:
The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is
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entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle: Capture-DR: The run test/idle state is used to execute tests. The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused.
Shift-DR:
Update-DR:
Capture-IR:
Shift-IR:
Update-IR:
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The TDO output is enabled during states Shift-DR and ShiftIR. Otherwise, it is tri-stated. Boundary Scan Instructions The following is a description of the standard instructions. Each instruction selects an serial test data register path between input, TDI, and output, TDO. BYPASS The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to bypass the device. The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input TDI and output TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan
EXTEST
SAMPLE
IDCODE
STCTEST
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register. The code can then be shifted out on output TDO using the Shift-DR state. Table 10 - Instruction Register
Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Identification Register Length - 32 bits Version number - 0x0 Part Number - 0x5347 Manufacturer's identification code - 0x0CD Device identification - 0x053470CD Boundary Scan Register The boundary scan register is made up of 139 boundary scan cells, divided into input observation (in_cell), output (out_cell), and bidirectional (io_cell) cells. These cells are detailed in the Figures 22, 23, 24 and 25. The first 32 cells form the ID code register, and carry the code 0x053470CD. The cells are arranged as follows:
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Table 11
Pin/ Enable Bit A[7:0]1 ALE CSB WRB RDB RSTB D[7:0] PIP[3:0] POP[3:0] OENB2 INTB HIZ3 TDAT[15:0] xoff tsoc txprty[1:0] twrenb tfclk bus8 tgfc tca tcp tpoh tpohen tprdi tpais tfp tpohfp tpohclk ttohen
Register Cell Type I.D. Bit(s) Pin/ Enable Register Bit IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IO_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL in_cell in_CELL in_CELL in_CELL in_CELL in_CELL IN_CELL out_CELL out_CELL In_CELL in_CELL in_CELL in_CELL IN_CELL out_cell out_celL in_cell 00000101 0 0 1 1 0 10001110 0001 1001 1 0 1 txcn txdp txdn tohfp tsdclk tbyp rbyp rxdon rxdop los rsow rsuc lof rsdclk rsd lrdi rlow rowclk rld rldclk lais rohfp groclk rtohfp rtohclk rtoh rpoh rpohfp rpohclk prdi 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 out_CELL OUT_CELL OUT_CELL OUT_CELL out_CELL in_cell in_CELL out_CELL out_CELL OUT_CELL out_CELL out_CELL out_CELL OUT_CELL out_CELL OUT_CELL out_CELL OUT_CELL out_CELL OUT_CELL out_CELL OUT_CELL out_CELL OUT_CELL out_CELL OUT_CELL OUT_CELL OUT_CELL out_cell out_cell Cell Type I.D. Bit(s)
138-131 130 129 128 127 126 125-118 117-114 113-110 109 108 107 106-91 90 89 88-87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
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Pin/ Enable
Register Bit
Cell Type
I.D. Bit(s)
Pin/ Enable
Register Bit
Cell Type
I.D. Bit(s)
ttoh ttohclk ttohfp gtoclk tld tlow tsow tsuc tlrdi tlais TLDCLK TOWCLK TsD TXcp
72 71 70 69 68 67 66 65 64 63 62 61 60 59
in_cell out_cell out_cell out_cell in_cell in_cell in_cell in_cell in_cell in_cell out_cell out_cell in_cell out_cell
-
pais lop RFCLK RRDENB tsen RGFC RCP LCD RSOC rdat[15:0] rxprty[1:0] rdatenb4 rca
28 27 26 25 24 23 22 21 20 19-4 3-2 1 0
out_cell out_cell in_cell in_cell in_cell out_cell out_cell out_cell out_cell out_cell out_cell out_cell out_cell
-
Notes: 1. A[7] is the first bit of the boundary scan chain. 2. OENB signal will set the bidirectional D[7:0] pins to an output when set low. 3. When set high, TCA, TCP TPOHFP TPOHCLK, TTOHCLK, TTOHFP , , , GTOCLK, TLDCLK, TOWCLK, TXC+/-, TXD+/-, TOHFP TSDCLK, RXDO+/-, , LOS, RSOW, RSUC, LOF, RSDCLK, RSD, LRDI, RLOW, ROWCLK, RLD, RLDCLK, LAIS, ROHFP GROCLK, RTOHFP RTOHCLK, RTOH, RPOH, , , RPOHFP RPOHCLK, PRDI, PAIS, LOP RGFC, RCP LCD, RCA, POP[3:0] , , , and INTB will be set to high impedance. 4. When set high, RDAT[15:0], RXPRTY[1:0] and RSOC will be set to high impedance.
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Figure 19
IDCODE
- Input Observation Cell (IN_CELL)
Scan Chain Out
Input Pad
G1 G2 SHIFT-DR
INPUT to internal logic
I.D. Code bit CLOCK-DR
12 1 2 MUX 12 12
Scan Chain In
D C
In this diagram and those that follow, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the centre of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the table above.
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Figure 20
- Output Cell (OUT_CELL)
S can Chain Out
EXT EST OUT PUT or Enable from s ys t em logic IDCODE S HI F T - DR
G 1 1 G 1 G 2 12 1 2 MUX 12 12 D C D C 1
OUT PUT or Enable
MUX
I.D. code bit CL OCK -DR UPDAT E- DR
S can Chain In
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Figure 21
- Bidirectional Cell (IO_CELL)
Scan Chain Out INPUT to internal logic
EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin
G1 1 G1 G2 12 1 2 MUX 12 12 1
MUX
OUTPUT to pin
D C
D C
I.D. code bit CLOCK-DR UPDATE-DR
Scan Chain In
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13 13.1
FUNCTIONAL TIMING Overhead Access Figure 22 RTOHFP
A1 byte A1 byte A1 byte A2 byte A2 byte
- Transport Overhead Extraction **** **** ****
E2 byte E2 byte
RTOHCLK
RTOHFP A1 byte RTOHCLK
B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
A1 byte
RTOH
The Transport Overhead Extraction timing diagram (Figure 22) illustrates the transport overhead extraction interface. The transport overhead extraction clock, RTOHCLK is nominally a 5.184 MHz (1.728 MHz for an STS-1 stream) clock and is derived from the recovered line clock, GROCLK. The entire 9 row by 9 (or 3) column transport overhead structure is extracted and serialized on RTOH over a frame period (125 s).
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Figure 23
OHFP
- Transport Overhead Orderwire and User Channel Extraction
ROWCLK RSOW RLOW RSUC
B1
B2
B3
B4 E1, F1, E2
B5
B6
B7
B8
approx 750 ns
OHFP ROWCLK
The Transport Overhead Orderwire and User Channel Extraction diagram (Figure 23) shows the relationship between the RSOW, RSUC and RLOW serial data outputs and their associated clock, ROWCLK. ROWCLK is a 72 kHz 50% duty cycle clock that is gapped to produce a 64 kHz nominal rate and is aligned as shown in the timing diagram. The E1, F1 and E2 bytes shifted out of the S/UNIPLUS on RSOW, RSUC and RLOW in the frame shown are extracted from the corresponding transport overhead channels in the previous frame.
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Figure 24
- Transport Overhead Data Link Clock and Data Extraction 125 s
RSDCLK RSD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 approx. 2 MHz DLCLK bursts RLDCLK RLD
RLDCLK
RLD
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
The Transport Overhead Data Link Clock and Data Extraction timing diagram (Figure 24) shows the relationship between the RSD, and RLD serial data outputs, and their associated clocks, RSDCLK and RLDCLK. RSDCLK is a 216 kHz, 50% duty cycle clock that is gapped to produce a 192 kHz nominal rate. RLDCLK is a 2.16 MHz, 67%(high)/33%(low) duty cycle clock that is gapped to produce a 576 kHz nominal rate. RSD (RLD) is updated on the falling RSDCLK (RLDCLK) edge. The D1-D3, and D4-D12 bytes shifted out of the S/UNI-PLUS in the frame shown are extracted from the corresponding receive line overhead channels in the previous frame.
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Figure 25 RPOHFP
- Path Overhead Extraction ****
J1 byte B3 byte C2 byte G1 byte F2 byte
**** ****
Z4 byte Z5 byte
RPOHCLK
J1 byte RPOHCLK RPOHFP RPOH
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1
B3 byte
B2 B3 B4 B5 B6 B7 B8
B1
The Path Overhead Extraction Timing Diagram (Figure 25) illustrates the path overhead extraction interface. The path overhead extraction clock, RPOHCLK is nominally a 576 kHz clock, and is derived from the recovered line clock, GROCLK. The entire path overhead (the complete 9 byte structure) is extracted, serialized and output on RPOH over a frame time.
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Figure 26 TTOHFP
- Transport Overhead Insertion ****
A1 byte A1 byte A1 byte A2 byte A2 byte
**** ****
E2 byte E2 byte
TTOHCLK
A1 byte TTOHCLK TTOHFP TTOH TTOHEN
A1 byte
B8
B1
B2 B3 B4 B5 B6 B7 B8
B1
B2 B3 B4 B5 B6 B7 B8
B1
The transport overhead insertion timing diagram (Figure 26) illustrates the transport overhead insertion interface. Output TTOHCLK is nominally a 5.184 MHz clock (1.728 MHz for an STS-1 stream) and is used to update output TTOHFP and to sample inputs TTOH and TTOHEN. The value sampled on , TTOHEN during the first overhead bit position of a given set of overhead bytes determines whether the values sampled on TTOH are inserted in the transmit stream. TTOHEN is held high during the bit 1 position of the first A1 byte in the TTOH stream. The eight bit values sampled on input TTOH during the first A1 byte period are inserted in the first A1 byte position in the transmit stream. Similarly, TTOHEN is held low during the bit 1 position of the second A1 byte. The default value (F6H) is inserted in the second A1 byte position in the transmit stream. An error insertion feature is also provided for the B1, H1, H2, and B2 byte positions. When TTOH is held high during any of the bit positions corresponding to these bytes, the corresponding bit is inverted before being inserted in the
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transmit stream (TTOHEN must be sampled high during the first bit position to enable the error insertion mask). Figure 27 - Transport Overhead Orderwire and User Channel Insertion
TOHFP TOWCLK
TSOW TSUC TLOW
B1
B2
B3
B4 E1, F1, E2
B5
B6
B7
B8
approx 750 ns
TOHFP TOWCLK
The Transport Overhead Orderwire and User Channel Insertion diagram (Figure 27) shows the relationship between the TSOW, TLOW and TSUC serial data inputs and their associated clock TOWCLK. TOWCLK is a 72 kHz 50% duty cycle clock that is gapped to produce a 64 kHz nominal rate and is aligned as shown in the timing diagram. The E1, E2 and F1 bytes shifted into the S/UNIPLUS on TSOW, TLOW and TSUC in the frame shown are inserted in the corresponding transport overhead channels in the next frame.
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Figure 28
- Transport Overhead Data Link Clock and Data Insertion 125 s
TSDCLK TSD B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
approx. 2 MHz DLCLK bursts TLDCLK TLD
TLDCLK
TLD
B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
The Transport Overhead Data Link Clock and Data Insertion timing diagram (Figure 28) shows the relationship between the TSD, and TLD serial data inputs, and their associated clocks, TSDCLK and TLDCLK respectively. TSDCLK is a 216 kHz, 50% duty cycle clock that is gapped to produce a 192 kHz nominal rate. TLDCLK is a 2.16 MHz, 67%(high)/33%(low) duty cycle clock that is gapped to produce a 576 kHz nominal rate. TSD (TLD) is sampled on the rising TSDCLK (TLDCLK) edge. The D1-D3, and D4-D12 bytes shifted into the S/UNIPLUS in the frame shown are inserted in the corresponding transport overhead channels in the following frame.
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Figure 29 TPOHFP
- Path Overhead Insertion ****
J1 byte B3 byte C2 byte G1 byte F2 byte
**** ****
Z4 byte Z5 byte
TPOHCLK
J1 byte TPOHCLK TPOHFP TPOH TPOHEN
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1
B3 byte
B2 B3 B4 B5 B6 B7 B8
B1
The Path Overhead Insertion Timing Diagram (Figure 29) illustrates the path overhead insertion interface. Output TPOHCLK is nominally a 576 kHz clock, and is used to update output TPOHFP and to sample inputs TPOH and , TPOHEN. In the figure, TPOHEN is held high throughout the eight bit positions of the J1 byte. The eight bit values sampled on input TPOH are inserted in the J1 byte position in the transmit stream. If TPOHEN was low during any of the 8 bit locations, the internally generated bit values of the corresponding bit positions would be inserted in the J1 byte. For the B3 byte position, an error insertion feature is provided. TPOHEN is held high during bit positions 2, 5, 6, 7, and 8 of the B3 byte. The values sampled on input TPOH are used as an error mask in the corresponding bit positions (2, 5, 6, 7, and 8) of the B3 byte in the transmit stream. If TPOH and TPOHEN are high during a bit location, the corresponding bit of the internally generated B3 byte is inverted before transmission.
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13.2
GFC Access Figure 30 - GFC Extraction Port
GROCLK RGFCE[3:0]=1111B RCP RGFC
GFC[0] GFC[3] CELL N-1 CELL N GFC[2] CELL N GFC[1] CELL N GFC[0] CELL N
RGFCE[3:0]=1010B RCP RGFC
GFC[1] CELL N-1 GFC[3] CELL N GFC[1] CELL N
The GFC Extraction Port Diagram (Figure 30) illustrates the relationship between the receive cell pulse, RCP signal and the receive serial GFC output. The RCP signal identifies the most significant GFC bit in the GFC field of a cell header. Whether a GFC bit is output or not is control by the RGFCE[3:0] bits in the RACP GFC Control register. Figure 31 GTOCLK TCP TGFC
X GFC[3] CELL N GFC[2] CELL N GFC[1] CELL N GFC[0] CELL N X
- GFC Insertion Port
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The GFC Insertion Port Diagram (Figure 31) illustrates the relationship between the transmit cell pulse, TCP output and the transmit generic flow control, TGFC input. The MSB (GFC[3]) of the four bit GFC code on the TGFC input is identified using the TCP output. The S/UNI-PLUS accumulates the code and transmits the code in the next transmit cell. If the next transmit cell is an idle/unassigned cell, the GFC code provided in the Idle/Unassigned Cell Header Pattern register is overwritten. If the next transmit cell is read from the FIFO, the GFC code passed through the FIFO is overwritten. 13.3 Drop Side Receive Interface Figure 32 - Receive Synchronous FIFO, TSEN=0
RFCLK RRDENB RCA RSOC RDAT[15:0] RXPRTY[1:0]
XX XX W1 W2
**** ****
RCALEVEL=0
**** **** **** ****
W(n-5) W(n-4) W(n-3)
Read Ignored
W(n-2)
W(n-1)
W(n)
The Receive Synchronous FIFO Timing, TSEN=0 Diagram (Figure 32) illustrates the operation of the drop side receive interface with tristating disabled. The S/UNI-PLUS indicates a cell is available by asserting the receive cell available output, RCA. RCA remains high until the receive FIFO is near empty (four words remaining), empty or if an error condition is detected. Selection of empty and near empty is made using the RCALEVEL0 bit in the RACP Interrupt Enable/Control register. For the near empty option, RCA transitions low four words before the last word of the last cell is read from the FIFO. RCA remains low for a minimum of one RFCLK clock cycle and then can transition high to indicate that there are additional cells available in the FIFO.
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Figure 33
- Receive Synchronous FIFO, TSEN=1
RFCLK RRDENB RCA RSOC RDAT[15:0] RXPRTY[1:0]
W1 W2
**** **** **** **** **** ****
W(n-5) W(n-4) W(n-3) W(n-2) W(n-1) W(n)
The Receive Synchronous FIFO Timing, TSEN=1 Diagram (Figure 33) illustrates the operation of the drop side receive interface with tristating enabled. 13.4 Drop Side Transmit Interface Figure 34 - Transmit Synchronous FIFO
**** **** **** ****
XX XX W1 W2 XX W3
TFCLK TWRENB TCA TSOC TDAT[15:0] TXPRTY[1:0]
**** ****
W(n-4)
W(n-3)
W(n-2)
W(n-1)
W(n)
W1
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The Transmit Synchronous FIFO Timing Diagram (Figure 34) illustrates the operation of the drop side transmit interface. The S/UNI-PLUS indicates that there is space available in the transmit FIFO by asserting the transmit cell available output, TCA. TCA remains high until the transmit FIFO is almost full, full or if an error condition is detected. Almost full implies that the transmit FIFO can accept at most an additional four writes. Selection between almost full and full is made using the TACP FIFO Control register. If TCA is asserted high and the downstream is ready to write a word, the downstream device should assert TWRENB low. At anytime, if the downstream does not have a word to write, it can deassert TWRENB.
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14
ABSOLUTE MAXIMUM RATINGS Table 12 - S/UNI-PLUS Absolute Maximum Ratings -40C to +85C -40C to +125C -0.5V to +6.0V -0.5V to V DD+0.5V 1000 V 100 mA 20 mA +230C +150C
Ambient Temperature under Bias Storage Temperature Supply Voltage Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature
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15
D.C. CHARACTERISTICS TC = -40C to +85C, VDD = 5 V 5% (Typical Conditions: TC = 25C, VDD = 5 V) Table 13 Symbol VDD AVD VIL VPIL - S/UNI-PLUS D.C. Characteristics Parameter Power Supply Power Supply Input Low Voltage (TTL Only) Input Low Voltage (PECL Only) VIH VPIH Input High Voltage (TTL Only) Input High Voltage (PECL Only) VPSWG AVD - 1.0 AVD - 1.8 2.0 AVD Volts - 1.6 VDD +0.5 AVD Volts - 0.8 mV Volts Min 4.75 4.75 -0.5 Typ 5 5 Max 5.25 5.25 0.8 Units Volts Volts Volts Guaranteed Input LOW Voltage Input LOW Voltage referenced to TAVD3, RAVD3, or RAVD4 Guaranteed Input HIGH Voltage Input HIGH Voltage referenced to TAVD3, RAVD3, or RAVD4 |VPIH - VPIL| Conditions
Input Voltage Swing 600 (RXD+/-, RRCLK+/, TRCLK+/- Only)
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Symbol VOL
Parameter Output or Bidirectional Low Voltage
Min
Typ 0.1
Max 0.4
Units Volts
Conditions IOL = -6 mA for outputs TXD+/-, TXC+/-. IOL = -4 mA for outputs GTOCLK, GROCLK, RDAT[15:0], RSOC, RCA, TCA, and RXPRTY[1:0]. IOL = -2 mA for all others, Note 3
VOH
Output or Bidirectional High Voltage
VDD 4.7 - 1.0
Volts
IOH = 6 mA for outputs TXD+/-, TXC+/-. IOH = 4 mA for outputs GTOCLK, GROCLK, RDAT[15:0], RSOC, RCA, TCA, and RXPRTY[1:0]. IOH = 2 mA for all others, Note 3
VT+ VTVTH IILPU IIHPU IIL IIH CIN
Reset Input High Voltage Reset Input Low Voltage Reset Input Hysteresis Voltage Input Low Current Input High Current Input Low Current Input High Current Input Capacitance
3.5 0.6 1.0 100 -10 -10 -10 450 0 0 0 5 525 +10 +10 +10
Volts Volts Volts A A A A pF VIL = GND, Notes 1, 3 VIH = VDD, Notes 1, 3 VIL = GND, Notes 2, 3 VIH = VDD, Notes 2, 3 Excluding Package, Package Typically 2 pF
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Symbol COUT CIO IDDOP
Parameter Output Capacitance Bidirectional Capacitance Operating Current Processing Cells (RFCLK = TFCLK = 51.84 MHz)
Min
Typ 5 5 175
Max
Units pF pF
Conditions Excluding Package, Package Typically 2 pF Excluding Package, Package Typically 2 pF VDD = 5.25 V, Outputs Unloaded, TXD+/- = RXD+/- = 155.52 Mbit/s TXD+/- = RXD+/- = 51.84 Mbit/s
220
mA
100 Notes on D.C. Characteristics:
170
mA
1. Input pin or bidirectional pin with internal pull-up resistor. 2. Input pin or bidirectional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. Typical values are given as a design aid. The product is not tested to the typical values given in the data sheet.
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MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (TC = -40C to +85C, VDD = 5 V 5%) Table 14 Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH - Microprocessor Interface Read Access (Figure 35) Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tristate Valid Read Negated to Output Tristate Min 10 5 10 10 20 0 5 80 20 50 Max Units ns ns ns ns ns ns ns ns ns ns
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Figure 35
- Microprocessor Interface Read Timing
tSAR
A[7:0] tS ALR
Valid
Address
tHAR tHALR
tV L ALE tS LR (CSB+RDB)
tHLR
tZ INTH INTB
tPRD D[7:0]
tZ RD
Valid Data
Notes on Microprocessor Interface Read Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals.
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4. Microprocessor Interface timing applies to normal mode register accesses only. 5. In non-multiplexed address/data bus architecture's, ALE should be held high, parameters tSALR, tHALR, tVL, tHLR and tSLR are not applicable. 6. Parameter tHAR is not applicable if address latching is used. 7. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 8. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. Table 15 Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR - Microprocessor Interface Write Access (Figure 36) Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 10 20 10 10 20 0 5 5 5 40 Max Units ns ns ns ns ns ns ns ns ns ns
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Figure 36
- Microprocessor Interface Write Timing
A[7:0] tS ALW tV L ALE tSAW (CSB+WRB)
Valid Address
tH ALW tS LW tHLW
tVWR
tH AW
tS DW D[7:0]
tH DW
Valid Data
Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. Microprocessor Interface timing applies to normal mode register accesses only. 3. In non-multiplexed address/data bus architecture's, ALE should be held high, parameters tSALW, tHALW, tVL, tHLW and tSLW are not applicable. 4. Parameter tHAW is not applicable if address latching is used. 5. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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6. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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S/UNI-PLUS TIMING CHARACTERISTICS (TC = -40C to +85C, VDD = 5 V 5%) Table 16 Symbol - Line Side Receive Interface (Figure 37) Description RRCLK+/RRCLK- Duty Cycle 51.84 or 155.52 MHz (RBYP high) 19.44 or 6.48 MHz (RBYP low) RXD+/RXD- Operating Frequency STS-3c/STM-1 (RBYP high) STS-3c/STM-1 (RBYP low) STS-1 (RBYP high) STS-1 (RBYP low) RRCLK+/RRCLK- Frequency Tolerance tSRXD RXD+/RXD- Setup time to RRCLK+/RRCLK- (RBYP asserted high.) RXD+/RXD- Hold time to RRCLK+/RRCLK- (RBYP asserted high.) 51 -20 1 155 156 156 52 52 +20 Mbit/s Mbit/s Mbit/s Mbit/s ppm ns 45 30 55 70 % Min Max Units
tHRXD
1.5
ns
Note:
The specification may be relaxed to +/- 50 ppm if the S/UNI-PLUS is not loop timed, or for applications that do not require this timing accuracy. If loop timing is enabled, the tighter tolerance is required to meet the SONET free run accuracy specification under loss of signal conditions. Frequency tolerance is measured with respect to the receive stream on RXD+/- when clock recovery is enabled (RBYP is low).
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Figure 37
- Line Side Receive Interface Timing
RRCLK+ RRCLKtS RXD RXD+ RXDtH RXD
Table 17 Symbol tPLOF tPLOS tPLAIS tPLRDI tPLOP tPPAIS PPRDI tPLCD
- Receive Alarm Output (Figure 38) Description GROCLK Low to LOF Valid GROCLK Low to LOS Valid GROCLK Low to LAIS Valid GROCLK Low to LRDI Valid GROCLK Low to LOP Valid GROCLK Low to PAIS Valid GROCLK Low to PRDI Valid GROCLK Low to LCD Valid Min -5 -5 -5 -5 0 0 0 0 Max 15 15 15 15 20 20 20 20 Units ns ns ns ns ns ns ns ns
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Figure 38
- Receive Alarm Output Timing
GROCLK tP LOF LOF tP LOS LOS tP LAIS LAIS tP LRDI LRDI tP LOP LOP tP PAIS PAIS tP PRDI PRDI tP LCD LCD
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Table 18 Symbol tPRTOH tPRTOHFP tPROW tPRSD tPRLD tPRPOH tPRPOHFP
- Receive Overhead Access (Figure 39) Description RTOHCLK Low to RTOH Valid RTOHCLK Low to RTOHFP Valid ROWCLK Low to RSOW, RSUC, RLOW Valid Prop Delay RSDCLK Low to RSD Valid RLDCLK Low to RLD Valid RPOHCLK Low to RPOH Valid RPOHCLK Low to RPOHFP Valid -10 -15 -15 -15 -15 10 5 5 5 5 ns ns ns ns ns Min -15 -15 Max 5 5 Units ns ns
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Figure 39
- Receive Overhead Access Timing
RTOHCLK tP RTOH RTOH tP
RTOHFP
RTOHFP
RPOHCLK tP RPOH RPOH tP RPOHFP RPOHFP
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ROWCLK tP ROW RSOW RSUC RLOW
RSDCLK tP RSD RSD
RLDCLK tP RLD RLD
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Table 19 Symbol tPRCP tPRGFC Figure 40
- Receive GFC Access (Figure 40) Description GROCLK Low to RCP Valid GROCLK Low to RGFC Valid - Receive GFC Access Timing Min 1 1 Max 20 20 Units ns ns
GROCLK tP RCP RCP tP RGFC RGFC
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Table 20 Symbol
- Line Side Transmit Interface (Figure 41) Description TRCLK+/TRCLK- Duty Cycle 51.84 or 155.52 MHz (TBYP high) 19.44 or 6.48 MHz (TBYP low) TRCLK+/TRCLK- Operating Frequency STS-3c/STM-1 (TBYP high) STS-1 (TBYP high) 19.44 MHz Nominal (TBYP low) 6.48 MHz Nominal (TBYP low) TRCLK+/TRCLK- Frequency Tolerance 19.375 6.375 -20 -2 -3 -2 156 52 19.5 6.5 +20 2 2 3 MHz MHz MHz MHz ppm ns ns ns 45 30 55 70 % Min Max Units
tPTXDdiff tPTXDneg tPTXDpos Note:
TXC+/TXC- Low to TXD+/TXD- Valid (STS-1 only) TXC+ Low to TXD+ Valid (STS-1 only) TXC- High to TXD+ Valid (STS-1 only)
The specification may be relaxed to +/- 50 ppm for LAN applications that do not require this timing accuracy. The tighter tolerance is required to meet the SONET free run accuracy specification.
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Figure 41
- Line Side Transmit Interface Timing
TXC+ TXCtP TXD+ TXDTXDdiff
TXC+ tP TXD+ TXD-
TXDneg
TXCtP TXD+ TXD-
TXDpos
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Table 21 Symbol tSTLAIS tHTLAIS tSTLRDI tHTLRDI tSTPAIS tHTPAIS tSTPRDI tHTPRDI
- Transmit Alarm Input (Figure 42) Description TLAIS Set-up time to GTOCLK TLAIS Hold time to GTOCLK TLRDI Set-up time to GTOCLK TLRDI Hold time to GTOCLK TPAIS Set-up time to GTOCLK TPAIS Hold time to GTOCLK TPRDI Set-up time to GTOCLK TPRDI Hold time to GTOCLK Min 10 5 10 5 10 5 10 5 Max Units ns ns ns ns ns ns ns ns
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Figure 42
- Transmit Alarm Input Timing
GTOCLK tS TLAIS TLAIS tS TLRDI TLRDI tS TPAIS TPAIS tS TPRDI TPRDI tH TPRDI tH TPAIS tH TLRDI tH TLAIS
Table 22 Symbol tPTTOHFP tPTPOHFP tSTTOH tHTTOH tSTTOHEN tHTTOHEN
- Transmit Overhead Access (Figure 43) Description TTOHCLK Low to TTOHFP Valid TPOHCLK Low to TPOHFP Valid TTOH Set-up time to TTOHCLK TTOH Hold time to TTOHCLK TTOHEN Set-up time to TTOHCLK TTOHEN Hold time to TTOHCLK Min -15 -15 25 25 25 25 Max 5 5 Units ns ns ns ns ns ns
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Symbol tSTOW tHTOW tSTSD tHTSD tSTLD tHTLD tSTPOH tHTPOH tSTPOHEN tHTPOHEN Figure 43
Description TSOW, TSUC, TLOW Set-up Time to TOWCLK TSOW, TSUC, TLOW Hold Time to TOWCLK TSD Set-up Time to TSDCLK TSD Hold Time to TSDCLK TLD Set-up Time to TLDCLK TLD Hold Time to TLDCLK TPOH Set-up time to TPOHCLK TPOH Hold time to TPOHCLK TPOHEN Set-up time to TPOHCLK TPOHEN Hold time to TPOHCLK - Transmit Overhead Access Timing
Min 25 25 25 25 25 25 25 25 25 25
Max
Units ns ns ns ns ns ns ns ns ns ns
TTOHCLK tP TTOHFP TTOHFP
TPOHCLK tP TPOHFP TPOHFP
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TTOHCLK tS TTOH tS
TTOHEN
TTOH
tH
TTOH
tH
TTOHEN
TTOHEN
TPOHCLK tS TPOH tS
TPOHEN
TPOH
tH
TPOH
tH
TPOHEN
TPOHEN
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TOWCLK tS TSOW TSUC TLOW tH
TOW
TOW
TSDCLK tS TSD tH
TSD
TSD
TLDCLK tS TLD tH
TLD
TLD
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Table 23 Symbol tPTCP tSTGFC tHTGFC Figure 44
- Transmit GFC Access (Figure 44) Description GTOCLK Low to TCP Valid TGFC Set-up time to GTOCLK TGFC Hold time to GTOCLK - Transmit GFC Access Timing Min 1 10 0 Max 20 Units ns ns ns
GTOCLK tP
TCP
TCP tS
TGFC
tH
TGFC
TGFC
Table 24 Symbol
- Drop Side Receive Interface (Figure 45, Figure 46) Description RFCLK Frequency RFCLK Duty Cycle 40 4 1 1 1 14 14 Min Max 50 60 Units MHz % ns ns ns ns
tSRRDENB tHRRDENB tPRCA tPRSOC
RRDENB Set-up time to RFCLK RRDENB Hold time to RFCLK RFCLK High to RCA Valid RFCLK High to RSOC Valid
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Symbol tPRDAT tPRXPRTY tPRFCLK tZRFCLK Figure 45
Description RFCLK High to RDAT[15:0] Valid RFCLK High to RXPRTY[1:0] Valid RFCLK High to Output Enable (TSEN high) RFCLK High to Output Tristate (TSEN high)
Min 1 1 1 1
Max 14 14 14 14
Units ns ns ns ns
- Drop Side Receive Interface Timing, TSEN = 0
RFCLK tS RRDENB tH RRDENB RRDENB
tP RDAT RDAT[15:0] tP RXPRTY RXPRTY[1:0]
tP RCA RCA
tP RSOC RSOC
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Figure 46
- Drop Side Receive Interface Timing, TSEN = 1
RFCLK TSEN=1 RRDENB tPRFCLK RDAT[15:0] RXPRTY[1:0] RSOC tZRFCLK Valid Data
Table 25 Symbol
- Drop Side Transmit Interface (Figure 47) Description TFCLK Frequency TFCLK Duty Cycle 40 4 1 4 1 4 1 4 1 1 14 Min Max 50 60 Units MHz % ns ns ns ns ns ns ns ns ns
tSTWRENB tHTWRENB tSTDAT tHTDAT tSTXPRTY tHTXPRTY tSTSOC tHTSOC tPTCA
TWRENB Set-up time to TFCLK TWRENB Hold time to TFCLK TDAT[15:0] Set-up time to TFCLK TDAT[15:0] Hold time to TFCLK TXPRTY[1:0] Set-up time to TFCLK TXPRTY[1:0] Hold time to TFCLK TSOC Set-up time to TFCLK TSOC Hold time to TFCLK TFCLK High to TCA Valid
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Figure 47
- Drop Side Transmit Interface
TFCLK tS
TWRENB
tH
TWRENB
TWRENB tS
TDAT
tH
TDAT
TDAT[15:0] tS tH
TXPRTY TXPRTY
TXPRTY[1:0] tS
TSOC
tH
TSOC
TSOC tP TCA TCA
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Table 26 Symbol
- JTAG Port Interface (Figure 48) Description TCK Frequency TCK Duty Cycle 40 50 50 50 50 2 50 Min Max 1 60 Units MHz % ns ns ns ns ns
tSTMS tHTMS tSTDI tHTDI tPTDO
TMS Set-up time to TCK TMS Hold time to TCK TDI Set-up time to TCK TDI Hold time to TCK TCK Low to TDO Valid
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Figure 48
- JTAG Port Interface Timing
TCK tS TMS TMS tS TDI TDI tH TDI tH TMS
TCK tP TDO TDO
Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input.
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3. When a set-up time is specified between a PECL input and a PECL clock, the set-up time is the time in nanoseconds from the crossing point of the differential input to the crossing point of the differential clock. 4. When a hold time is specified between a PECL input and a PECL clock, the hold time is the time in nanoseconds from the crossing point of the differential clock to the crossing point of the differential input. Notes on Output Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are specified with a 50 pF load on the outputs, except for TXD+/- and TXC+/-. Maximum output propagation delays for TXD+/- and TXC+/- are specified with a 30 pF load. 3. Differential output propagation delay time is the time in nanoseconds from the crossing point of the reference signal to the crossing point of the output.
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ORDERING AND THERMAL INFORMATION Table 27 PART NO. PM5347-RI Table 28 PART NO. PM5347-RI - S/UNI-PLUS Ordering Information DESCRIPTION 208 Pin Plastic Quad Flat Pack (PQFP) - S/UNI-PLUS Thermal Information AMBIENT TEMPERATURE -40C to 85C Theta Ja 28 C/W Theta Jc 10 C/W
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MECHANICAL INFORMATION Figure 49 - 208 Pin Plastic Quad Flat Pack (R Suffix):
D D1
208
A
1
Pin 1 Designator
e
E E1
8-12 DEG.
8-12 DEG.
A2
SEE DETAIL A
0-10 DEG. STANDOFF
NOTES: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSIONS SHOWN ARE NOMINAL WITH TOLERANCES AS INDICATED. 3) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE, 0.25 ABOVE SEATING PLANE.
A
.25
A1
SEATING PLANE C 0-7 DEG L b C
0.13-0.23
LEAD COPLANARITY ccc C
DETAIL A
PACKAGE TYPE: 208 PIN METRIC PLASTIC QUAD FLATPACK-MQFP BODY SIZE: 28 x 28 x 3.49 MM Dim. Min. Nom. Max. 4.07 0.48 A 3.64 A1 0.25 A2 3.39 3.49 3.59 D 30.40 30.60 30.80 D1 27.90 28.00 28.10 E 30.40 30.60 30.80 E1 27.90 28.00 28.10 L 0.50 0.60 0.75 0.50 e b 0.17 0.22 0.27 0.10 ccc
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NOTES
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NOTES
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PMC-941033 (R6) ref PMC-940306 (P8) Issue date: June 1998
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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